Scan Chain Clock Layout for Hold-Time-Safe Semiconductor Testing
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Solution Overview
Problem
As the circuit scale increases in semiconductor integrated circuits, particularly in image sensors, there is an increase in circuit scale and power consumption, leading to potential hold time violations during scan data testing.
Innovation Solution
A semiconductor integrated circuit design is implemented with a scan chain configured to transfer data in a backward direction, utilizing clock buffers to delay the clock signal and incorporating lockup latches to adjust delay times, reducing the need for additional buffers and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the circuit scale increases to accommodate more pixels and larger logic circuits, then the functionality and processing capability improve, but the circuit scale and power consumption increase
Solution Approach 1:
The circuit is divided into multiple logic circuits that can be independently tested, with each logic circuit containing n data holding circuits. The scan chain is segmented to transfer data between these logic circuits through delay adjusting units, allowing modular testing without requiring a monolithic large-scale test structure.
Solution Approach 2:
The scan chain transfers data in a backward direction opposite to the clock signal's forward direction. This dimensional reversal in data flow creates an alternative pathway for testing that avoids the constraints of traditional forward-direction scan chains, enabling efficient testing of large-scale circuits without proportionally increasing circuit scale.
2Adaptability or versatility
If the circuit scale increases to accommodate more pixels and larger logic circuits, then the functionality and processing capability improve, but the power consumption increases
Solution Approach 1:
The test infrastructure is segmented into modular components (logic circuits, data holding circuits, delay adjusting units) that can be activated independently. This allows testing of specific circuit portions without powering the entire large-scale circuit, reducing overall power consumption during testing.
Solution Approach 2:
By reversing the scan chain data transfer direction to backward flow, the patent creates an efficient testing mechanism that reduces the need for additional buffering infrastructure. This dimensional change in data flow optimizes power usage by minimizing the activation of power-consuming buffer circuits.
3Reliability
If additional buffers are added to guarantee data hold in the scan chain, then the data hold reliability improves, but the circuit scale increases
Solution Approach 1:
Delay adjusting units serve as intermediary components between logic circuits in the scan chain. These units provide the necessary delay adjustment to guarantee data hold without requiring multiple additional buffers, thus maintaining reliability while minimizing circuit scale increase.
Solution Approach 2:
The patent changes the delay parameter dynamically by selecting different delay amounts from the delay adjusting units based on the specific testing requirements. This parameter adjustment approach ensures data hold reliability without permanently increasing circuit scale through fixed buffer additions.
4Reliability
If additional buffers are added to guarantee data hold in the scan chain, then the data hold reliability improves, but the power consumption increases
Solution Approach 1:
The delay adjusting units act as efficient intermediaries that provide precise delay control without the power overhead of multiple buffer stages. This intermediary approach maintains data hold reliability while minimizing power consumption compared to traditional buffer-based solutions.
Solution Approach 2:
By dynamically adjusting the delay parameter through selectable delay amounts rather than using fixed buffer chains, the system achieves data hold reliability with minimal power consumption. The parameter change approach avoids the continuous power draw associated with multiple active buffers.
Data Source
AI summary
A semiconductor integrated circuit in which a plurality of logic circuits are arranged. Each logic circuit comprises n data holding circuits, a scan chain to transfer scan data, and a clock line including a plurality of clock buffers. The clock signal from the clock line is supplied to the n data holding circuits. In a forward direction from a first data holding circuit in the n data holding circuits to an nth data holding circuit in the holding circuits, the clock signal with a large delay amount is supplied from the clock line to a data holding circuit on a downstream side. The scan chain transfers the scan data in a backward direction from the nth data holding circuit to the first data holding circuit. The scan data is transferred between the logic circuits via a first delay adjusting unit.