Scan Chain Hold Time Violation Detection via Segmented Pattern Testing
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Solution Overview
Problem
As technology nodes shrink, scan chain defects such as hold-time violations become more common, leading to yield loss and inaccurate evaluation of integrated circuits, as conventional testing methods struggle to reliably transfer data and localize these defects within scan chains.
Innovation Solution
A real-time interpretative scan pattern generation method that applies specific input patterns, determines a safe voltage for loading and unloading data, and uses fault bit processing to detect and localize hold-time defects, allowing for efficient identification and correction of hold-time violations in scan chains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional testing methods are used to test scan chains, then testing can be performed, but hold-time violations cannot be reliably detected or localized
Solution Approach 1:
The patent segments the scan chain into individual scan cells and uses separate pattern streams for different segments. By applying patterns to specific segments and observing outputs from corresponding segments, the method can localize hold-time violations to specific cells within the chain, transforming an undifferentiated testing approach into a segmented, diagnosable system.
Solution Approach 2:
The patent changes the parameters of test patterns by applying different data sequences (e.g., alternating 0s and 1s, all 0s, all 1s) and varying pattern lengths. By observing how different pattern parameters affect the output and comparing expected versus actual results, the method can detect and localize hold-time violations that would be invisible with conventional single-pattern testing.
2Productivity
If scan chains are used in nanometer geometry designs, then circuit functionality is achieved, but hold-time violations become more common
Solution Approach 1:
The patent implements feedback by comparing the actual scan chain output with the expected output based on applied patterns. When discrepancies are detected (indicating hold-time violations), the system uses this feedback information to identify problematic cells and adjust testing strategies, creating a closed-loop testing approach that continuously improves detection accuracy.
Solution Approach 2:
The patent performs preliminary actions by applying specific test patterns designed to force transitions at every bit position before conducting the actual hold-time violation detection. This preliminary pattern application prepares the scan chain in known states and establishes baseline expectations, enabling more reliable detection of subsequent violations.
3Quantity of substance
If more flip-flops are added to scan chains, then test coverage increases, but the likelihood of defects increases
Solution Approach 1:
The patent divides the large scan chain into manageable segments, each tested with dedicated pattern streams. This segmentation transforms the difficulty of testing a large monolithic chain into the simpler task of testing multiple smaller segments, allowing defects to be localized to specific regions rather than searching through the entire chain.
Solution Approach 2:
The patent applies local quality by using different test patterns for different segments of the scan chain. Each segment receives patterns optimized for detecting violations in that specific region, allowing the testing system to adapt to local characteristics and提高 detection effectiveness without requiring a completely different approach for the entire chain.
Data Source
AI summary
A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects, and, if possible, localizing, and ameliorating hold time defects in a scan chain.