Scan Chain Test Clocking with Inverted Head Registers
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Solution Overview
Problem
Conventional testing methods for digital electronic circuits, such as ATPG, Transition Fault, and IDDQ tests, are time-consuming, often taking several seconds to achieve desired fault coverage, limiting the efficiency of digital circuit testing in applications like automotive-grade products.
Innovation Solution
Increasing the ATPG shift clock frequency by incorporating additional head and tail registers sensitive to inverted clock signals, allowing for faster scan test execution and reducing test time through improved timing margins and parallelization of scan chains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the ATPG shift clock frequency is increased to reduce testing time, then testing speed improves, but timing margins and signal integrity may deteriorate
Solution Approach 1:
The patent divides the single clock signal into multiple phase-shifted clock signals (e.g., CLK, CLK1, CLK2) with different phase relationships. This segmentation allows different scan registers to be clocked at different effective times, improving timing margins and enabling higher test frequencies without compromising signal integrity.
Solution Approach 2:
The patent introduces head registers that are clocked before the main scan registers, performing preliminary actions to capture test patterns earlier in the cycle. This preliminary clocking action allows the main scan registers to operate at higher frequencies while maintaining proper timing margins.
2Reliability
If the scan sequence length is increased to achieve desired fault coverage, then fault detection capability improves, but testing time increases
Solution Approach 1:
The patent implements periodic clocking of scan registers with phase-shifted clock signals, enabling parallel progression of scan sequences through multiple registers. This periodic action with overlapping clock cycles allows longer scan sequences to be processed in less time, maintaining fault coverage while reducing testing duration.
Solution Approach 2:
The patent makes the clocking mechanism dynamic by using adjustable phase-shifted clock signals that can be optimized for different test scenarios. This dynamic clocking allows the system to adaptively balance between scan sequence length and testing time based on the specific fault detection requirements.
Data Source
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Figure 3A~4B
AI summary
An electronic circuit (10') comprises: - a combinational circuit block (100) having a set of input pins (IN1, ..., INn) configured to receive input digital signals and a set of output pins (OUT1, ..., OUTm) configured to provide output digital signals as a function of the input digital signals received, - a test input pin (SCAN_IN) configured to receive a test input signal and a test output pin (SCAN_OUT) configured to provide a test output signal as a function of the test input signal received, - a set of scan registers (SRI, SR2, SR3) selectively (SE) couplable (M1, M2, M3) either to the combinational circuit block (100) or to one another so as to form a scan chain of scan registers serially coupled between the test input pin (SCAN_IN) and the test output pin (SCAN_OUT), the scan registers in the set of scan registers being sensitive to a clock signal (CLK), and - at least one input register (HI, H2) coupled between the test input pin (SCAN_IN) and a first scan register (SRI) of said scan chain, wherein the at least one input register (HI, H2) is sensitive to an inverted replica (20) of said clock signal (CLK). The scan registers in the set of scan registers (SRI, SR2, SR3) are active on one of the rising edges or falling edges of said clock signal (CLK) provided thereto, and said at least one input register (HI, H2) is active on the other of the rising edges or falling edges of said clock signal (CLK).