Scan Chain Partitioning to Block Logic Locking Key Leakage
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Solution Overview
Problem
Integrated circuits (ICs) are vulnerable to malicious modifications and counterfeiting due to untrusted third-party involvement in the design and manufacturing flow, with existing obfuscation techniques becoming ineffective against SAT-based attacks, especially when ICs are partitioned into smaller circuit blocks, and the scan chain remains a critical security risk.
Innovation Solution
The proposed technique secures the scan chain by creating a logical partition between functional and test modes of a circuit, using logic locking and a charge accumulation circuit to prevent unauthorized access and detect attempts to bypass the test mode, without modifying the scan chain structure, thereby preventing SAT and ScanSAT attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic locking is applied to secure the combinational logic cone, then IP theft and reverse engineering are prevented, but area overhead and power consumption increase
Solution Approach 1:
The circuit is divided into two distinct operational modes: functional mode for normal operation with logic locking applied to the combinational logic cone, and test mode for scan chain operations. This segmentation allows security measures to be applied only where necessary during functional mode, while test mode uses a different key for scan chain access, thereby securing the logic cone without permanently increasing area overhead.
Solution Approach 2:
The patent changes the operational parameters by introducing a mode selection mechanism that switches between functional and test modes. In functional mode, the logic locking key is active; in test mode, a separate scan chain key is used. This parameter change allows the same hardware to provide security against different types of attacks without requiring additional security circuitry for both modes simultaneously.
2Ease of operation
If the scan chain is used for testing, then testability is improved, but SAT-based attacks and key leakage become possible
Solution Approach 1:
The scan chain is secured by segmenting the key space into two separate keys: one for functional mode operation and another for test mode operation. The mode selection logic ensures that the scan chain key is only active during test mode, preventing SAT-based attacks that would otherwise leverage scan chain access to recover the functional key through iterative learning.
Solution Approach 2:
A mode selection mechanism acts as an intermediary between the scan chain and the key input, controlling which key is applied based on the operational mode. This intermediary prevents direct access to the functional key through the scan chain by inserting a control layer that selects the appropriate key based on mode signals.
3Reliability
If logic locking is applied to the entire circuit, then security is improved, but area overhead and power consumption increase significantly
Solution Approach 1:
The security mechanism is segmented to apply logic locking only to the combinational logic cone during functional mode, while the scan chain uses a separate key during test mode. This segmentation avoids applying security measures to the entire circuit simultaneously, thereby reducing the overall area overhead and power consumption compared to full-circuit logic locking.
Solution Approach 2:
Instead of applying logic locking to the entire circuit, the patent applies partial action by securing only the critical combinational logic cone during functional mode. The scan chain is secured separately during test mode using a different key, which is sufficient to prevent key leakage without the excessive overhead of securing every part of the circuit with the same mechanism.
Data Source
AI summary
A proposed technique allows for the security of the logic cone through logic locking and secures the outputs of the circuit from the scan chain without modifications to the structure of the scan chain. Since the oracle responses in test mode do not correspond to the functional key, satisfiability (SAT) attacks are not able to leverage the responses from the scan chain. In addition, a charge accumulation circuit is developed to prevent and detect any attempt to enter the partitioned test mode while the correct circuit responses are still stored within the registers.