Scan Chain Initialization with Disparate Latches
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Solution Overview
Problem
Current integrated circuit designs require multiple cycles to initialize different types of latches, necessitating sequential grouping and testing, which is time-consuming and inefficient, especially when all latches need to be initialized simultaneously within a single cycle.
Innovation Solution
Incorporating a multiplexer and an OR gate between disparate latches allows for simultaneous initialization of all latch types in a single cycle by using the data port to load initial values, eliminating the need for sequential grouping and reducing test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential grouping and initialization of different latch types is used, then each latch type can be properly initialized, but the test time and initialization cycles increase
Solution Approach 1:
The patent merges the initialization of multiple disparate latch types (D flip-flops, T flip-flops, JK flip-flops) into a single unified scan chain that can be initialized simultaneously in one cycle. The multiplexer circuit allows different latch types to share common initialization control signals, eliminating the need for sequential grouping and reducing test time while maintaining proper initialization of each latch type.
Solution Approach 2:
The patent implements a universal initialization approach where a single scan chain and multiplexer circuit can handle multiple types of latches (D, T, JK flip-flops) with different initialization requirements. The multiplexer provides multi-functional control by routing appropriate initialization signals to different latch types based on their specific needs, allowing one system to serve multiple purposes.
2Productivity
If multiple scan chains are designed in parallel, then test time is reduced, but device complexity increases
Solution Approach 1:
The patent combines multiple latch types into a single scan chain using a multiplexer, eliminating the need for multiple parallel scan chains. This merging approach maintains high test efficiency by allowing simultaneous initialization of all latches in one cycle while reducing device complexity by removing redundant scan chain infrastructure.
Data Source
AI summary
Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.