Scan Chain Masking Circuitry for Semiconductor Test Security

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Solution Overview

Problem

Existing semiconductor devices face security vulnerabilities due to thorough scan cell coverage revealing sensitive information, making them susceptible to reverse engineering and scan-based security attacks.

Innovation Solution

Implementing security logic with masking circuitry and monitoring and enforcement circuitry to obscure scan data and detect potential configuration changes that could compromise security, using initial and infinite masking modes to protect scan data output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If scan cell coverage is made thorough to verify functionality and correctness, then manufacturing quality and reliability are improved, but security vulnerabilities increase due to exposure of sensitive information

Engineering Contradiction:
Improvemanufacturing qualityVSAvoidsecurity vulnerabilities
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces masking circuitry as an intermediary component between the scan cells and the external testing equipment. This masking circuitry acts as a mediator that processes and obfuscates the scan data before it is output, allowing thorough scan cell coverage for manufacturing verification while preventing direct exposure of sensitive information to external systems.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the scan data output into different components by introducing separate masking circuitry that can independently process and obfuscate specific portions of the scan data. This segmentation allows the system to maintain comprehensive scan coverage for quality verification while selectively protecting sensitive information through the masking function.

Inventive Principle:
Principle #1Segmentation

2Object-affected harmful factors

If masking circuitry is added to obscure scan data and prevent reverse engineering, then security is improved, but device complexity increases

Engineering Contradiction:
ImprovesecurityVSAvoidcircuit complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The masking circuitry is designed to be self-regulating through the monitoring and enforcement circuitry that automatically detects configuration changes and activates masking modes as needed. The system monitors itself for security threats and self-corrects by enabling masking functionality, reducing the need for external intervention and simplifying the overall control mechanism despite the added complexity.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent implements different masking modes (initial masking mode and infinite masking mode) that can be activated based on detected configuration changes. By changing the operational parameters of the masking circuitry dynamically rather than using a fixed complex design, the system achieves enhanced security while managing complexity through parameter-based control.

Inventive Principle:
Principle #35Parameter changes

3Object-affected harmful factors

If monitoring and enforcement circuitry is implemented to detect configuration changes, then security is improved, but manufacturing cost increases

Engineering Contradiction:
ImprovesecurityVSAvoidmanufacturing cost
Core Design Contradiction:
Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The monitoring and enforcement circuitry implements a feedback mechanism that continuously monitors device configuration and automatically triggers masking modes when unauthorized changes are detected. This feedback-based approach provides robust security protection while keeping the manufacturing process straightforward, as the system self-regulates without requiring complex external monitoring or manual intervention.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20260063714A1Scan Test Security for Semiconductor Devices
Publication Date: 2026.03.05 NVIDIA CORP
  • US20260063714A1 patent drawing
  • US20260063714A1 patent drawing
  • US20260063714A1 patent drawing

AI summary

A semiconductor device includes a scan data output and a scan chain having length n. Scan data bits appear sequentially at the scan data output responsive to a scan clock when the device is in a scan mode. Initial masking circuitry is operable to obscure, responsive to the device transitioning from a non-scan mode to the scan mode, a first n bits of the scan data appearing at the scan data output and not to obscure n+1st and subsequent bits of the scan data appearing at the scan data output. Infinite masking circuitry is operable to obscure, responsive to an infinite masking trigger, all scan data bits appearing at the scan data output until a reset of the device occurs. Monitoring and security enforcement circuitry is operable to detect a configuration change and to generate the infinite masking trigger if the detected change corresponds to a potential security risk.