Scan Chain Ordering Optimization via Physical Placement
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Solution Overview
Problem
Existing scan chain ordering methods in circuit designs involving latches are not optimized and result in inefficient wire connections, requiring messy pin additions and updates, which are time-consuming and resource-intensive.
Innovation Solution
A method for optimizing scan chain ordering by dedicating a scan input pin and a scan output pin for each latch, generating digital labels to identify optimal wiring arrangements, and creating digital layouts that minimize wire length, allowing for seamless schematic and layout updates without additional pin or wire complexities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If scan chain is wired according to hardware description language convention (Verilog or VHDL), then correspondence for logic checking is improved, but wire length and resource usage increase
Solution Approach 1:
Instead of wiring scan chains according to logical hierarchy (conventional approach), the patent inverts the approach by wiring according to physical placement proximity. The scan chain connects latches based on their physical locations in the layout, creating shorter wires while maintaining logic checking capability through automated mapping.
Solution Approach 2:
The patent changes the wiring parameter from logical ordering to physical proximity ordering. By using placement-driven netlists that consider physical coordinates of latches, the scan chain wiring automatically optimizes wire length while maintaining correspondence for logic checking through the mapping between logical and physical representations.
2Length of stationary object
If scan chain is made placement driven to minimize wires, then wire length is reduced, but schematic complexity and update time increase
Solution Approach 1:
The system performs self-service by automatically generating placement-driven scan chain wiring from the placement database. The tool independently analyzes physical latch locations, determines optimal scan chain ordering, and updates both schematic and layout without requiring manual designer intervention, thus reducing schematic complexity despite placement-driven optimization.
Solution Approach 2:
The patent performs preliminary actions by establishing the scan chain wiring order based on placement information before finalizing the schematic. The placement database is used early in the process to determine optimal wiring, and this predetermined ordering is then applied to generate the final schematic, avoiding later complex modifications.
3Length of stationary object
If manual updates are made to schematic to reflect location driven scan chain, then wire length is minimized, but time and resource consumption increase
Solution Approach 1:
The patent replaces the manual mechanical process of updating schematics with an automated computer-based system. The tool automatically reads placement information, calculates optimal scan chain ordering, and updates the schematic database without manual intervention, eliminating the time-consuming manual update process while achieving placement-driven wire minimization.
Solution Approach 2:
The system implements feedback by continuously referencing the placement database to verify and update scan chain wiring. The automated tool monitors placement changes and automatically adjusts the schematic accordingly, creating a closed-loop system that maintains consistency between physical layout and logical representation without manual intervention.
Data Source
AI summary
A method for optimizing a scan chain ordering in circuit designs in an electronic computer-aided design system is provided. The method comprising: creating a schematic representative of a circuit design having a first cell and a second cell, the first cell and the second cell each having latches therein; creating a scan input pin and a scan output pin for each of the latches in the first cell and the second cell on the schematic; generating a first label on the schematic to provide a first wiring arrangement for the latches in the circuit design, the first wiring arrangement identifies a first order to which the scan input of each of the latches is wired to the scan output of another one of the latches; creating a layout representative of the circuit design; generating a first scan chain having a first length on the layout based on the first wiring arrangement; creating a second scan chain from the first scan chain on the layout, the second scan chain having a second length less than the first length of the first scan chain; and generating a second label on the schematic based on the second scan chain, the second label provides a second wiring arrangement for the latches in the circuit design, the second wiring arrangement identifies a second order to which the scan input of each of the latches is wired to the scan output of another one of the latches.