Scan Chain Stitching by Physical Placement to Cut Wire Length
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Solution Overview
Problem
Existing scan chain stitching methods result in long and congested wires, increased capacitance, and power dissipation due to unnecessary wire traverses and metal layer changes, which hinder chip performance and size optimization.
Innovation Solution
A method that stitches scan flipflops based on their physical location rather than logic hierarchy, minimizing wire length and congestion by optimizing the scan stitching order and routing on a single metal layer, avoiding unnecessary crossovers and layer changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If scan flipflops are stitched together based on logic hierarchy, then the scan chain can be formed, but wire length becomes excessively long and congestion increases
Solution Approach 1:
The patent performs scan chain stitching after physical placement is complete, using the actual physical locations of flipflops to determine stitching order. This preliminary action based on final placement data eliminates the need for long wire traverses that occur when stitching is done before placement, directly reducing wire length and congestion.
Solution Approach 2:
The patent changes the ordering parameter from logic hierarchy to physical location. By sorting flipflops based on their physical coordinates (x, y positions) rather than their logical hierarchy, the scan chain follows the physical layout, minimizing wire length and avoiding congestion in specific regions.
2Adaptability or versatility
If scan chains are routed with frequent metal layer changes, then routing flexibility is improved, but capacitance and power dissipation increase
Solution Approach 1:
The patent applies different routing strategies to different regions based on local density. In high-density regions, it minimizes layer changes and wire traverses. The solution allows uniform SE net routing across layers while optimizing scan chain routing locally to reduce capacitance and power dissipation in congested areas.
3Ease of manufacture
If scan flipflops are stitched in arbitrary order, then stitching simplicity is maintained, but wire congestion and capacitance increase
Solution Approach 1:
The patent performs preliminary sorting of flipflops based on their physical locations before stitching. This preliminary ordering action ensures that consecutive flipflops in the scan chain are physically adjacent or nearby, minimizing wire length without complicating the stitching implementation.
Solution Approach 2:
The patent changes the ordering parameter from arbitrary or logic-based to physics-based (physical location). By sorting flipflops according to their x, y coordinates, the scan chain naturally follows the physical layout, reducing wire length and capacitance while maintaining implementation simplicity.
Data Source
AI summary
The scan flipflops on a semiconductor chip are stitched together to form one or more scan chains, located in one or more standard cell placement regions, after the optimal physical location of each scan flip-flop has been determined. As a result, the total length of the scan chain wires is substantially reduced, thereby reducing on-chip wiring congestion, flip-flop load capacitance, and flipflop power dissipation.