Hierarchical Scan Chain Planning for Balanced Chip-Level Testability
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Solution Overview
Problem
The formation of chip level scan chains in hierarchical integrated circuit designs is often sub-optimal due to limitations in block scan chain port locations and size, leading to unbalanced scan chains in terms of physical length and number of elements.
Innovation Solution
The method involves partitioning the hierarchical integrated circuit design based on the number and size of scan chains, determining physical block locations, and placing elements to optimize block scan port placement, with scan chains entering and exiting each tile only once to minimize block scan ports and achieve balanced chip level scan chains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If chip level scan chains are formed based on block scan chains with fixed port locations, then the design follows hierarchical methodology, but the scan chains become unbalanced in physical length and number of elements
Solution Approach 1:
The chip level scan chain formation is segmented into multiple passes: first pass forms scan chains using block scan chains with fixed port locations, second pass adjusts and rebalances the scan chains by moving scan elements between chains. This segmentation allows maintaining hierarchical design benefits while achieving balanced scan chains.
Solution Approach 2:
The patent performs preliminary scan chain formation based on block scan chains before final optimization. The initial scan chains are created using available block scan ports, then subsequent passes adjust the configuration to achieve balance, ensuring that hierarchical constraints are respected while achieving optimal results.
2Ease of operation
If block scan chain port locations are fixed, then block design is simplified, but the number of block scan ports increases and chip level scan chains become sub-optimal
Solution Approach 1:
The patent merges multiple block scan chains into chip level scan chains by strategically connecting block scan output ports to block scan input ports through glue logic. This merging reduces the effective number of independent block scan ports needed while maintaining design simplicity.
Solution Approach 2:
Glue logic acts as an intermediary between block scan chains, enabling flexible connection and routing of scan elements. This intermediary layer allows optimization of chip level scan chains without modifying block internal structures, maintaining block design simplicity while reducing overall complexity.
3Productivity
If scan chains are formed without considering physical block locations, then design process is simpler, but scan chain physical length becomes unbalanced
Solution Approach 1:
The patent applies local quality by considering physical block locations when forming and optimizing scan chains. Scan elements are selected and positioned with awareness of their physical locations, creating scan chains with more uniform physical lengths. This localized optimization maintains reasonable design process efficiency while achieving balanced scan chain lengths.
Data Source
AI summary
A scan chain planning method uses physical data with a hierarchical design to optimize chip level scan chains. Specifically, location data of physical blocks is used to determine optimal partitioning of the hierarchical design to balance chip level scan chains and reduce the number block scan ports by determining optimal locations for the block scan ports. Actual layout of the scan chains is based on the locations of the block scan ports and the number of scan elements determined by the method for each block scan chain.