Scan Chain Power Limiting via Segmented Clock Gating
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Solution Overview
Problem
Current chip testing methods face significant challenges in reducing power dissipation during the test phase, particularly in low-power designs, leading to increased risk of overheating and data corruption, as existing techniques either fail to guarantee power dissipation within a specified budget or result in substantial area overhead and complexity.
Innovation Solution
A structured methodology that employs an adjacent-fill technique to minimize flip-flop transitions during scan-in and uses a segment-selection circuit to limit the number of flip-flops changing state during capture, ensuring power dissipation remains within a specified budget without clock gating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If clock gating is used to reduce power dissipation during normal operation, then power dissipation is reduced, but test becomes impossible because circuits cannot be scanned when clock is switched off
Solution Approach 1:
The circuit is divided into multiple segments with different clock gating control. During normal operation, clock gating is applied to unused segments to save power. During test, the scan path is configured to bypass clock gating controls, allowing scanning to proceed while other segments remain clock-gated. This segmentation allows simultaneous power saving and testability.
Solution Approach 2:
The clock gating control is made dynamic by providing different control signals for normal operation versus test mode. A test mode signal enables the scan path to override clock gating, while during normal operation the clock gating controls power saving. This dynamic switching resolves the contradiction between power saving and testability.
2Ease of operation
If clock gating is bypassed during test to enable scanning, then testability is maintained, but power dissipation increases substantially
Solution Approach 1:
The circuit is divided into multiple segments with different clock gating control. During normal operation, clock gating is applied to unused segments to save power. During test, the scan path is configured to bypass clock gating controls, allowing scanning to proceed while other segments remain clock-gated. This segmentation allows simultaneous power saving and testability.
Solution Approach 2:
The clock gating control is made dynamic by providing different control signals for normal operation versus test mode. A test mode signal enables the scan path to override clock gating, while during normal operation the clock gating controls power saving. This dynamic switching resolves the contradiction between power saving and testability.
3Loss of energy
If prior art techniques manipulate test patterns or scan-chain logic to reduce power dissipation, then power dissipation is reduced, but area overhead and complexity increase substantially
Solution Approach 1:
The existing clock gating infrastructure is made multi-functional by using it for both power saving during normal operation and power reduction during test (when combined with scan path configuration). This eliminates the need for separate power reduction mechanisms during test, avoiding additional area overhead and complexity.
Solution Approach 2:
The clock gating mechanism, already present for power saving, is leveraged to also reduce power during test operations. By configuring the scan path to work with existing clock gating rather than bypassing it entirely, the system uses its own existing infrastructure to solve the test power problem, avoiding additional complexity.
Data Source
AI summary
An embodiment provides a system for testing a circuit. During operation, the system scans-in input values into a first set of flip-flops. The outputs of the first set of flip-flops are coupled with the inputs of a circuit under test, the outputs of the circuit are coupled with the inputs of a set of multiplexers, and the outputs of the set of multiplexers are coupled with the inputs of a second set of flip-flops. Next, the system configures the set of multiplexers using a segment-selection circuit, which causes the outputs of the circuit to be coupled with the inputs of the second set of flip-flops. The system then captures the circuit's output values using the second set of flip-flops. Next, the system scans-out the circuit's output values using the second set of flip-flops. Finally, the system determines whether the chip has a fault using the output values.