Scan Chain Power Saving in Semiconductor Devices

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Solution Overview

Problem

Existing semiconductor devices face challenges in reducing power consumption due to unused functional blocks, as methods like input vector control require dedicated control circuits, leading to increased circuit scale and inefficiencies.

Innovation Solution

A semiconductor device configuration that includes a central processing device, logical circuits with scan chains, and a serial memory interface circuit, which acquires and sets a scan pattern for power saving, suppressing leakage currents without the need for additional control circuits, thereby reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If input vector control is used to suppress leakage current in unused functional blocks, then power consumption is reduced, but circuit scale increases due to dedicated control circuits

Engineering Contradiction:
Improvepower consumptionVSAvoidcircuit scale
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The scan chain is designed to serve dual purposes: performing test functions and controlling input vectors for power saving. By making the scan chain multi-functional, the patent eliminates the need for dedicated control circuits while achieving leakage current suppression in unused functional blocks, thus reducing power consumption without increasing circuit scale

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the test function and power control function into a single integrated system using the scan chain. The scan chain that was traditionally used only for testing is now combined with power management capabilities, allowing it to control input vectors and suppress leakage currents in unused blocks without requiring separate control circuitry

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If dedicated control circuits are added for input vector control, then leakage current suppression capability is improved, but device complexity increases

Engineering Contradiction:
Improveleakage current suppression capabilityVSAvoidcircuit scale
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The scan chain is designed to serve dual purposes: performing test functions and controlling input vectors for power saving. By making the scan chain multi-functional, the patent eliminates the need for dedicated control circuits while achieving leakage current suppression in unused functional blocks, thus reducing power consumption without increasing circuit scale

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The scan chain performs self-service by simultaneously executing test operations and power management functions. The same scan chain infrastructure that exists for testing is utilized to control the input vectors of unused functional blocks, allowing the system to manage its own power consumption without external or dedicated control circuits

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11422614B2Semiconductor device and control method of semiconductor device
Publication Date: 2022.08.23 KK TOSHIBA
  • US11422614B2 patent drawing
  • US11422614B2 patent drawing
  • US11422614B2 patent drawing

AI summary

A semiconductor device comprises a central processing device, a first logical circuit, and a serial memory interface circuit. The first logical circuit has a first scan chain in which a first scan pattern is set, is configured to suppress a leakage current when the first scan pattern for power saving is set in the first scan chain. The serial memory interface circuit is configured to acquire the first scan pattern for power saving from an external storage device. The leakage current of the first logical circuit is suppressed by transferring the first scan pattern for power saving acquired by the serial memory interface circuit to the first logical circuit and setting the first scan pattern for power saving in the first scan chain under control of the central processing device.