Dynamic Scan Chain Reconfiguration for Test-Per-Clock Efficiency

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Solution Overview

Problem

The existing test-per-scan and test-per-clock schemes in circuit testing are inefficient in terms of time and power consumption, with the test-per-scan scheme requiring excessive clock cycles for data shifting and the test-per-clock scheme experiencing high power dissipation due to constant scan chain activity.

Innovation Solution

A new test-per-clock scheme is introduced, where scan chains operate in dynamically partitioned and reconfigurable modes, including shifting-launching, capturing-compacting-shifting, and mission modes, allowing for efficient test pattern generation and response compaction, reducing power consumption by minimizing extrinsic circuit toggling and enabling higher fault coverage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If test-per-scan scheme is used, then test pattern shifting and response capturing are performed, but excessive clock cycles are required for data shifting increasing test time

Engineering Contradiction:
Improvetest timeVSAvoidtesting efficiency
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The scan chains are made dynamically reconfigurable, allowing them to switch between test-per-scan mode and test-per-clock mode with different operational configurations. This dynamic adaptability enables the system to optimize between thoroughness and speed depending on the testing phase and requirements.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The testing process alternates between periodic test-per-scan operations (for comprehensive fault detection) and test-per-clock operations (for rapid fault verification). This periodic switching between two testing methodologies balances the need for thorough testing with the need for reduced test time.

Inventive Principle:
Principle #19Periodic action

2Productivity

If test-per-clock scheme is used, then test pattern generation and response compaction are performed every clock cycle, but high power dissipation occurs due to constant scan chain activity

Engineering Contradiction:
Improvetesting efficiencyVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The scan chains are segmented into multiple groups that can be independently controlled and configured. Different groups can operate in different modes simultaneously, allowing the system to perform high-speed test-per-clock operations on some chains while keeping other chains in low-power test-per-scan mode or mission mode.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different portions of the scan chains are assigned different operational characteristics. Some scan chains are configured for test-per-clock operation with specific pattern generation requirements, while others are configured for test-per-scan or remain in mission mode. This local differentiation optimizes both power consumption and testing efficiency for each specific chain based on its function.

Inventive Principle:
Principle #3Local quality

3Loss of energy

If scan chains are reconfigured into different modes, then power consumption is reduced by minimizing circuit toggling, but system complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidsystem complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The scan chains are designed with multi-functionality, capable of operating in test-per-scan mode, test-per-clock mode, and mission mode. This universal design allows the same hardware resources to serve multiple purposes, reducing the need for separate dedicated circuits for each function and thereby limiting the increase in overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system incorporates dynamic reconfiguration capabilities that allow scan chains to switch between different operational modes as needed. This dynamic adaptability enables power optimization by placing scan chains in appropriate modes based on testing requirements, while the reconfiguration logic is integrated into the existing scan chain architecture to minimize added complexity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9347993B2Test generation for test-per-clock
Publication Date: 2016.05.24 SIEMENS INDUSTRY SOFTWARE INC
  • US9347993B2 patent drawing
  • US9347993B2 patent drawing
  • US9347993B2 patent drawing

AI summary

Aspects of the invention relate to test generation techniques for test-per-clock. Test cubes may be generated by adding constraints to a conventional automatic test pattern generator. During a test cube merging process, a first test cube is merged with one or more test cubes that are compatible with the first test cube to generate a second test cube. The second test cube is shifted by one bit along a direction of scan chain shifting to generate a third test cube. The third test cube is then merged with one or more test cubes in the test cubes that are compatible with the third test cube to generate a fourth test cube. The shifting and merging operations may be repeated for a predetermined number of times.