Scan Chain Reset Architecture for Low-Area Chip Initialization
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Solution Overview
Problem
Traditional microcircuit designs require extensive reset trees and per-flop reset logic, consuming significant area and power, and presenting timing challenges due to the need for full functional clock speeds during reset conditions.
Innovation Solution
The use of existing scan circuitry to shift reset data through scan chains, eliminating the need for high fan-out reset trees and per-flop reset circuitry, with clock control to optimize clock speeds and manage reset latency by forming scan chains and using control circuitry to sense reset conditions and control the shifting of reset data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional reset trees and per-flop reset logic are used, then each scannable flop can be reset to a known state, but the area and power consumption increase significantly
Solution Approach 1:
The scan chain is designed to serve dual purposes: it functions as both the test scanning path and the reset path. By making the scan chain universal, the patent eliminates the need for separate reset trees and per-flop reset logic, thereby reducing area while maintaining reliable reset capability for all scannable flops
Solution Approach 2:
The patent merges the reset function with the existing scan chain structure. Instead of having separate reset circuitry for each flop, the reset signal is combined with the scan chain to shift reset values through all flops serially, consolidating multiple reset paths into a single unified structure
2Speed
If traditional reset trees operate at full functional clock speeds, then reset can be performed quickly, but power consumption increases and timing challenges arise
Solution Approach 1:
The patent implements dynamic clock frequency adjustment based on operational mode. During reset operations, the clock frequency is reduced to match the slower scan chain timing, preventing excessive power consumption. During normal functional operation, the clock returns to full speed, optimizing performance. This dynamic adaptation resolves the contradiction between reset speed and power consumption
3Adaptability or versatility
If scan chains are made longer to include more scannable elements, then more flops can be reset, but reset latency increases
Solution Approach 1:
The patent segments the scan chain into multiple independent scan chains, each handling a subset of flops. This segmentation allows parallel reset operations across different chains, reducing overall reset latency while maintaining comprehensive coverage of all scannable elements. Each chain can be reset independently and simultaneously
Data Source
AI summary
Scan-based reset utilizes already existing design-for-test scan chains to reset control and logic circuitry upon reset conditions, such as power-up reset. Such utilization eliminates the need for expensive, high fan-out reset trees and per scan cell reset control logic, thus reducing chip area and power consumption. Additional power savings is achieved by controlling clock frequency during reset conditions. Limiting scan cell chain length and providing multiple chains reduces reset latency.