Scan-Chain Flip-Flop Resetting Without Dedicated Reset Circuitry
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional integrated circuit resetting methods require substantial area and power due to the presence of reset circuitry, leading to issues like current spikes and reset domain crossing, which are difficult to debug and inefficient in terms of power consumption.
Innovation Solution
The proposed solution involves electrically connecting flip-flops in a predefined series without a reset gate or associated circuitry, using a scan input gate to feed a bit string of identical bits to reset the flip-flops, thereby reducing area and power consumption by eliminating conventional reset networks and associated power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional reset circuitry is used to reset integrated circuits, then resetting functionality is achieved, but area consumption and power requirements increase substantially
Solution Approach 1:
The scan chain is designed to serve dual purposes: performing test operations and resetting the integrated circuit. By making the scan structure multi-functional, dedicated reset circuitry becomes unnecessary, thereby reducing area consumption while maintaining resetting functionality through the same scan infrastructure
Solution Approach 2:
The invention extracts and eliminates the dedicated reset circuitry from the integrated circuit design. By removing this separate functional block and integrating resetting capability into the existing scan chain, the overall area consumption is reduced while resetting functionality is preserved through the scan-based approach
2Reliability
If conventional reset circuitry is used to reset integrated circuits, then resetting functionality is achieved, but power consumption increases substantially
Solution Approach 1:
The scan chain is designed to serve dual purposes: performing test operations and resetting the integrated circuit. By making the scan structure multi-functional, dedicated reset circuitry becomes unnecessary, thereby reducing power consumption while maintaining resetting functionality through the same scan infrastructure
Solution Approach 2:
The invention merges the resetting function with the existing scan chain operations. By combining these two functions into a single operational pathway, the power consumption associated with separate reset circuitry is eliminated, as the same scan infrastructure handles both testing and resetting without requiring additional power resources
3Reliability
If reset network is used to reset all flip-flops, then resetting functionality is achieved, but current spikes occur due to simultaneous toggling
Solution Approach 1:
The scan-based resetting approach inherently introduces periodicity and control to the resetting process. By using the scan chain to sequentially or controlledly update flip-flop states, the simultaneous toggling that causes current spikes is avoided, as the scan structure naturally regulates the timing and sequence of state changes across different flip-flops
4Reliability
If conventional reset networks are used, then resetting functionality is achieved, but device complexity and difficulty of debugging increase
Solution Approach 1:
The invention extracts and eliminates the dedicated reset circuitry from the integrated circuit design. By removing this separate functional block and integrating resetting capability into the existing scan chain, the overall circuit complexity is reduced while resetting functionality is preserved through the scan-based approach
Solution Approach 2:
The scan chain is designed to serve dual purposes: performing test operations and resetting the integrated circuit. By making the scan structure multi-functional, dedicated reset circuitry becomes unnecessary, thereby reducing device complexity while maintaining resetting functionality through the same scan infrastructure
Data Source
AI summary
A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.