Scan Chain Ring Topology for Defect Diagnosis
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Solution Overview
Problem
Scan chains in VLSI circuits can fail, preventing proper testing of integrated circuits, as defects within the scan chains go undetected, leading to inefficiencies in yield ramping and production cycles.
Innovation Solution
A direct access scan chain architecture and method that allows for the identification of root causes of scan chain failures by shifting logic sequences through scan blocks, enabling direct data transfer between functioning and non-functioning scan chains to diagnose defects within scan blocks, regardless of defect type or location.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional scan chain testing is used, then testing of integrated circuit parts is performed, but defects in scan chains themselves go undetected, preventing proper diagnosis
Solution Approach 1:
The scan chain is divided into multiple scan blocks, each containing a storage element and switching device. This segmentation allows individual blocks to be tested independently by shifting test sequences through each block and comparing expected versus actual outputs, enabling precise defect location and diagnosis without requiring the entire scan chain to be functional.
Solution Approach 2:
A test sequence is introduced as an intermediary mechanism to diagnose scan chain defects. The test sequence is shifted through scan blocks and compared with expected values to identify defects. This intermediary approach enables detection of scan chain defects without requiring external complex testing equipment or disrupting normal circuit operation.
2Productivity
If scan chains are used for testing integrated circuit parts, then testing capability is provided, but the scan chains themselves may contain defects that prevent proper testing
Solution Approach 1:
The patent applies preliminary action by first testing scan blocks with known good functionality before using them to test the integrated circuit. Scan blocks are pre-diagnosed by shifting test sequences through them and verifying outputs. Only scan blocks that pass this preliminary test are used for actual circuit testing, ensuring testing reliability without requiring the entire scan chain to be defect-free.
Solution Approach 2:
The patent implements feedback by comparing the actual output of scan blocks with expected outputs during testing. When a discrepancy is detected, the system identifies the defective scan block and uses feedback from functioning scan blocks to diagnose the fault. This feedback mechanism enables continuous monitoring and diagnosis of scan chain health during the testing process.
3Device complexity
If conventional scan chain architecture is used, then simple structure is maintained, but defect diagnosis requires complex analysis and extended cycle time
Solution Approach 1:
By segmenting the scan chain into independent testable blocks, the patent enables parallel diagnosis of multiple blocks simultaneously. Each block can be tested independently using the same test sequence, allowing defects to be identified in parallel without requiring sequential analysis of the entire chain, thus reducing overall diagnosis cycle time.
Solution Approach 2:
The patent uses copying by creating a simplified test model of each scan block that can be independently analyzed. The test sequence acts as a copy that replicates the expected behavior of each block, allowing defects to be identified by comparing actual versus expected responses without requiring complex analysis of the original scan chain architecture.
Data Source
AI summary
A circuit includes a plurality of scan chains arranged in a ring network topology. Each scan chain includes a plurality of scan blocks, each of the plurality of scan blocks including a storage element and a switching device. Each switching device includes a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed, and a second input configured to receive one of a function logic signal or a test scan signal. The switching device configured to selectively couple the first input or the second input to an input of the storage element.