Scan Chain Comparison Circuit for Secure Chip Testing
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Solution Overview
Problem
Scan chains in chips compromise security by allowing hackers to retrieve data through test modes, enabling them to deduce logic circuit designs or steal user data.
Innovation Solution
Implementing a scan chain circuit with golden scan flip-flops and comparison circuits that compare actual operation results with predetermined results, outputting only comparison results to prevent data deduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a scan chain is designed in the chip to perform functional testing, then the testability of the chip is improved, but the security is decreased
Solution Approach 1:
The patent introduces a scan chain obfuscation circuit as an intermediary between the logic circuit and the external testing interface. This circuit includes scan flip-flops, comparison circuits, and obfuscation logic that mediates the test data flow, preventing direct observation of internal logic states while enabling functional testing. The intermediary transforms actual operation results into obfuscated comparison results, thus resolving the contradiction between testability and security.
Solution Approach 2:
The patent creates a copy of the logic circuit's operation results through the scan chain obfuscation circuit. Instead of directly outputting actual operation results, the system generates comparison results that are copies transformed through obfuscation logic. These copied and transformed results enable testing while preventing direct deduction of the original logic circuit design, thus maintaining both testability and security.
2Ease of operation
If actual operation result bit values are directly outputted through the scan chain, then testing is simplified, but hackers can deduce logic circuit design and steal user data
Solution Approach 1:
The patent changes the parameter of the output data from actual operation result bit values to obfuscated comparison result bit values. The comparison circuit compares actual results with predetermined values and outputs only the comparison results (match/mismatch indicators). This parameter change transforms sensitive data into non-sensitive test indicators, maintaining testing capability while preventing data leakage and logic circuit deduction.
3Object-affected harmful factors
If a comparison circuit and golden scan flip-flop are introduced to output comparison results instead of actual results, then security is improved, but device complexity increases
Solution Approach 1:
The patent segments the scan chain into multiple functional units: scan flip-flops for data storage, comparison circuits for result comparison, and obfuscation logic for security transformation. Each segment performs a specific function, making the overall system more manageable despite increased complexity. The segmentation allows systematic integration of security features without completely redesigning the entire scan chain architecture.
Data Source
AI summary
A scan chain circuit and an operation method thereof are provided. The scan chain circuit includes a plurality of scan chain units. Each of the scan chain units includes a plurality of input scan flip-flop (SFF) and a comparison circuit. After a plurality of input bit values are operated by a logic circuit, a plurality of actual operation result bit values are obtained. The comparison circuit is used to receive the actual operation result bit values and a plurality of predetermined operation result bit values. Each of the predetermined operation result bit values is each of a plurality of predetermined operation results after each of the input bit values is operated by the logic circuit. The comparison circuit compares the actual operation bit values and the predetermined operation result bit values, and then outputs a bits comparison result bit value.