Scan Chain Segmentation for Test Time Reduction
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Solution Overview
Problem
Complex integrated circuit designs face challenges in achieving efficient fault coverage and minimizing test cost due to increased test application time and sub-optimal test architectures, which are often sub-optimal for specific circuit designs.
Innovation Solution
A test design optimizer is used to develop candidate test designs based on the circuit design, generating test vectors and evaluating fault coverage, allowing for the selection of an optimal test architecture that customizes scan chain lengths, decompressor modes, and compression logic to minimize test time and data volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of flip-flops per scan chain is increased to achieve better fault coverage, then the test application time increases dramatically
Solution Approach 1:
The patent segments the scan chains into multiple parallel chains, distributing the total number of flip-flops across several chains rather than concentrating them in a single chain. This segmentation allows the test application time to be reduced by a factor equal to the number of parallel scan chains, while maintaining comprehensive fault coverage through exhaustive testing of all flip-flops across the segmented chains.
2Ease of manufacture
If conventional test architectures are used, then the test design is simple to implement, but the fault coverage is sub-optimal for specific circuit designs
Solution Approach 1:
The patent introduces a dynamic test architecture where scan chain configurations can be adapted based on the specific circuit design. The system allows for flexible assignment of flip-flops to scan chains and can dynamically adjust test parameters to optimize fault coverage for different circuit characteristics, moving from a static conventional approach to a dynamic adaptive approach.
Solution Approach 2:
The patent employs parameter changes by allowing variable scan chain lengths, different numbers of parallel chains, and adjustable test patterns based on the specific circuit design. The test architecture can modify parameters such as the number of scan chains, the distribution of flip-flops across chains, and test pattern generation to achieve optimal fault coverage for each specific circuit.
3Reliability
If more test patterns are generated to improve fault coverage, then the test data volume increases
Solution Approach 1:
The patent creates a universal test architecture that can efficiently generate test patterns for multiple types of faults using a single integrated framework. The same scan chain configuration and test pattern generation algorithm can be applied across different circuit designs and fault types, reducing the need for separate specialized test sequences and minimizing overall test data volume while maintaining comprehensive fault coverage.
Data Source
AI summary
Roughly described, a scan-based test architecture is optimized in dependence upon the circuit design under consideration. In one embodiment, a plurality of candidate test designs are developed. For each, a plurality of test vectors are generated in dependence upon the circuit design and the candidate test design, preferably using the same ATPG algorithm that will be used downstream to generate the final test vectors for the production integrated circuit device. A test protocol quality measure such as fault coverage is determined for each of the candidate test designs, and one of the candidate test designs is selected for implementation in an integrated circuit device in dependence upon a comparison of such test protocol quality measures. Preferably, only a sampling of the full set of test vectors that ATPG could generate, is used to determine the number of potential faults that would be found by each particular candidate test design.