Scan Chain Stitching for Test-Per-Clock Efficiency
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Solution Overview
Problem
The existing test-per-scan and test-per-clock schemes in circuit testing are inefficient in terms of time and power consumption, with the test-per-scan scheme requiring excessive clock cycles for data shifting and the test-per-clock scheme experiencing high power dissipation due to excessive circuit toggling.
Innovation Solution
The implementation of dynamically-partitioned reconfigurable scan chains using scan chain stitching techniques, where scan cells are assigned to partitions based on combinational paths and operated in different modes to optimize testing efficiency and reduce power consumption, allowing for more efficient test pattern application and response compaction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If test-per-scan scheme is used, then structured design-for-test methodology is achieved, but excessive clock cycles are required for data shifting
Solution Approach 1:
The scan chains are segmented into different groups (first group and second group) that can be independently configured and operated. This segmentation allows simultaneous operation of multiple scan chains in different modes, enabling parallel test pattern application and response capture, thereby reducing overall test time while maintaining the structured DFT methodology.
Solution Approach 2:
The scan chains are made dynamically reconfigurable, allowing them to switch between different operational modes (test-per-scan mode and test-per-clock mode) based on the specific testing requirements. This dynamic reconfiguration enables the system to optimize between structured testing approach and testing speed for different test scenarios.
2Reliability
If test-per-scan scheme is used, then controllability and observability are achieved, but shifting operations require much more clock cycles than actual testing
Solution Approach 1:
Scan chains are divided into segments that can operate independently in different modes. Some segments can perform rapid test-per-clock shifting while others maintain test-per-scan operation, allowing the system to achieve both high controllability/observability and reduced shifting time through parallel operations.
Solution Approach 2:
The scan chain system is designed to perform multiple functions: it can operate in traditional test-per-scan mode for high controllability and observability, and simultaneously in test-per-clock mode for rapid data shifting. This multi-functionality allows the same hardware structure to serve both reliability and speed requirements.
3Productivity
If test-per-clock BIST system is used, then test time efficiency is improved, but excessive circuit toggling causes high power dissipation
Solution Approach 1:
The scan chains are segmented into different operational groups, allowing only necessary portions of the circuit to toggle during testing. By dividing the system into first and second groups with different operational modes, the invention minimizes unnecessary circuit switching and reduces overall power dissipation while maintaining high test time efficiency.
Solution Approach 2:
Different parts of the scan chain system are assigned different operational characteristics: some segments operate in test-per-clock mode for high speed, while others operate in test-per-scan mode for lower power consumption. This local differentiation allows the system to optimize performance in critical areas while conserving energy in less critical areas.
4Productivity
If conventional test-per-clock BIST system is used, then new test pattern is applied at every test clock cycle, but all scan chains change contents every clock cycle causing excessive toggling
Solution Approach 1:
Scan chains are divided into first and second groups that can be independently controlled. During test-per-clock operation, only the necessary groups need to change contents at every clock cycle, while other groups can remain stable. This segmentation reduces the total number of toggling elements and consequently lowers power dissipation.
Solution Approach 2:
Instead of requiring all scan chains to change contents every clock cycle, the system applies partial action by allowing only specific groups to update at high speed while others update less frequently or remain stable. This partial updating approach maintains high test pattern application speed where needed while reducing unnecessary toggling and power consumption.
Data Source
AI summary
Various aspects of the present invention relate to scan chain stitching techniques for test-per-clock. With various implementations of the invention, a plurality of scan cell partitions are generated based on combinational paths between scan cells. Scan cells may be assigned to one or more pairs of scan cell partitions based on combinational paths between the scan cells. Each pair of the scan cell partitions comprises one stimuli partition and one compacting partition. Using the plurality of scan cell partitions generated, scan chains are formed based on at least information of combinational paths between scan cell partitions in the plurality of scan cell partitions. The formed scan chains are to be dynamically divided into three groups during a test, which are configured to operate in a shifting-launching mode, a capturing-compacting-shifting mode and a mission mode, respectively.