Scan Chain Storage Element Reducing ATPG Power
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Solution Overview
Problem
Integrated Circuits (ICs) face high power consumption and area requirements due to combinational logic toggling during automatic test pattern generation (ATPG) shift mode, leading to increased test time and costs, as well as unnecessary power loss in functional operations.
Innovation Solution
The development of scannable storage elements with input circuits and shifting circuits that selectively provide pull-up or pull-down logic signals, reducing toggling and power consumption by controlling scan output logic states based on scan enable inputs, thereby optimizing power and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan design is implemented by placing multiplexers in front of standard inputs to enable scan mode operation, then testability and scan chain functionality are improved, but power consumption increases due to complete design logic toggling during ATPG shift mode
Solution Approach 1:
The patent applies local quality by making the scan input logic state configurable at the individual flop level. Each flop can be assigned pull-up or pull-down logic based on its specific path requirements, rather than using a uniform approach across the entire design. This localized optimization reduces unnecessary toggling in combinatorial logic during ATPG shift mode while maintaining scan chain functionality.
Solution Approach 2:
The patent changes the parameter of logic state (pull-up or pull-down) for scan inputs based on the specific path requirements. By analyzing the scan chain and determining the appropriate logic state for each flop's scan input, the patent minimizes toggling in combinatorial logic during test mode while preserving the ability to perform functional operations. This parameter optimization directly reduces power consumption during ATPG shift operations.
2Productivity
If ATPG shift frequency is increased to reduce test time, then productivity is improved, but reliability deteriorates due to high IR drop and reliability issues caused by complete design logic toggling
Solution Approach 1:
The patent applies local quality by making the scan input logic state configurable at the individual flop level. Each flop can be assigned pull-up or pull-down logic based on its specific path requirements, rather than using a uniform approach across the entire design. This localized optimization reduces unnecessary toggling in combinatorial logic during ATPG shift mode while maintaining scan chain functionality.
Solution Approach 2:
The patent changes the parameter of logic state (pull-up or pull-down) for scan inputs based on the specific path requirements. By analyzing the scan chain and determining the appropriate logic state for each flop's scan input, the patent minimizes toggling in combinatorial logic during test mode while preserving the ability to perform functional operations. This parameter optimization directly reduces power consumption during ATPG shift operations.
3Reliability
If signal activity is allowed to propagate from D pin to SD pins of subsequent flops during functional operations, then functional correctness is maintained, but power consumption increases due to unnecessary signal toggling
Solution Approach 1:
The patent applies dynamics by making the scan input logic state configurable and changeable based on operational mode. During functional operations, the scan inputs can be set to a fixed logic state (pull-up or pull-down) to prevent unnecessary signal propagation and reduce power consumption, while during test mode, the scan inputs dynamically accept signal activity for proper test operation. This dynamic configuration allows the system to adapt its behavior to minimize power consumption in each operational context.
Data Source
AI summary
In an embodiment, a scannable storage element includes an input circuit for providing a first signal at first node based on a data input and a scan input, where the scan input is of pull-up logic in functional mode. The input circuit includes a first pull-up path comprising a switch receiving data input and a switch receiving scan enable input, and second pull-up path comprising a switch receiving scan input, first pull-down path comprising a switch receiving the scan enable input and a switch receiving the scan input, and second pull-down path comprising a switch receiving the data input. The storage element includes a shifting circuit configured to provide a second signal in response to the first signal at second node, and a scan output buffer coupled to the second node and configured to provide a scan output at a scan output terminal in response to the second signal.