Scan Chain Storage Element Synchronous Asynchronous Modes

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Solution Overview

Problem

The high power consumption during scan testing of integrated circuits, due to the need for large power grids and increased die area, poses a challenge in minimizing test time while maintaining efficient functional operation.

Innovation Solution

The implementation of a storage element in scan chains that can operate in both synchronous and asynchronous modes, allowing for reduced power consumption by distributing shift power and minimizing clock buffer delays, thereby reducing overall power usage during both test and functional operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If scan chains are configured as synchronous shift registers with common clock during scan test mode, then test time is minimized, but power consumption increases significantly

Engineering Contradiction:
Improvetest timeVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The storage element dynamically switches between synchronous and asynchronous modes based on operational requirements. During scan test mode, it operates asynchronously to reduce power consumption, while during functional operation mode, it operates synchronously to maintain timing precision. This dynamic mode switching resolves the contradiction between test time efficiency and power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the operational parameters of the storage element by introducing a request signal mechanism that controls when data is transferred. Instead of continuous synchronous clocking, the system uses request signals to trigger asynchronous data transfer, fundamentally changing the timing parameter from clock-driven to event-driven, thereby reducing power consumption during scan testing.

Inventive Principle:
Principle #35Parameter changes

2Power

If power grid size is increased to accommodate large scan test mode power consumption, then power delivery capability is improved, but die area and product costs increase

Engineering Contradiction:
Improvepower delivery capabilityVSAvoiddie area
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

The invention converts the harmful effect of high power consumption during scan testing into a beneficial asynchronous operation mode. By using request signals to trigger data transfer only when needed, the system reduces overall power consumption, thereby eliminating the need for oversized power grids and reducing die area requirements.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Measurement precision

If clock buffers are used to balance clock signals during synchronous operation, then timing precision is improved, but power consumption and device complexity increase

Engineering Contradiction:
Improvetiming precisionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The invention extracts the clock buffer component from the system by transitioning to asynchronous operation during scan test mode. Instead of using clock buffers to balance timing, the system uses request signals to coordinate data transfer between storage elements, eliminating the need for additional buffering hardware and its associated power consumption.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The request signal acts as an intermediary mechanism that replaces the clock buffer's timing coordination function. Instead of using clock buffers to synchronize data transfer, the request signal mediates between the data source and destination, triggering transfer only when both parties are ready, thereby achieving coordination without the power overhead of clock buffering.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Productivity

If multiple short scan chains are used in parallel instead of one long scan chain, then test time is reduced, but power consumption during scan testing increases

Engineering Contradiction:
Improvetest timeVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The invention segments the scan chain into multiple independent storage elements that can operate asynchronously. Each storage element processes data independently triggered by request signals, allowing parallel operation without the synchronized clock overhead. This segmentation enables both reduced test time through parallelism and reduced power consumption through asynchronous operation.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP3065136B1Semiconductor storage device for scan chain having synchronous and asynchronous modes
Publication Date: 2019.09.25 NXP USA INC
  • EP3065136B1 patent drawingFigure 1~2
  • EP3065136B1 patent drawingFigure 3
  • EP3065136B1 patent drawingFigure 4

AI summary

A method for performing scan testing using a scan chain having a plurality of storage elements is described. During a capture phase, each storage element of the scan chain stores data from a first data input of the storage element synchronously to a clock signal. And during a shift phase, a scan pattern is shifted into the scan chain in which each storage element stores data from a second data input of the storage element asynchronously with the clock signal.