Partitioned Scan Chain Test Controller Pin Reduction
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Solution Overview
Problem
Existing scan test technologies for integrated circuits with partitioned scan chains lack sufficient control over scan durations and require a large number of pins for external testing, which limits flexibility and efficiency in testing different partitions independently.
Innovation Solution
A test controller within the integrated circuit that allows independent control of scan durations for each partition, reduces the number of pins required by using serial to parallel and parallel to serial converters, and supports transition fault launch-on shift testing with registers to store and manage test vectors efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If partitioned scan chains are used to enable independent testing of partitions, then testability and power management are improved, but the number of pins required for external testing increases
Solution Approach 1:
Multiple scan chains are merged into a single shared physical pin structure. The patent implements a common scan-in pin that can sequentially receive test data for different partitions, and a common scan-out pin for retrieving results. Internal multiplexers route data between the single pin and multiple scan chains, eliminating the need for separate pins per partition while maintaining independent testability of each partition.
2Device complexity
If scan durations are controlled centrally for all partitions, then device complexity is reduced, but independence in scanning different partitions is lost
Solution Approach 1:
The scan control functionality is segmented into partition-specific control units, with each partition having its own control logic that can independently manage scan operations. The patent implements separate scan enable signals, clock controls, and duration management for each partition, allowing one partition to be scanned while another remains inactive or operates at different speeds, thus providing independent scan duration control for each partition.
3Ease of operation
If more pins are provided for each partition, then ease of operation for external testing is improved, but device complexity and pin count increase
Solution Approach 1:
The scan pins are designed with universal functionality to serve multiple partitions. The patent implements a single scan-in pin that can be configured to accept test data for any partition through internal routing, and a single scan-out pin that can output data from any partition. This multi-functional pin design maintains ease of external testing operation while minimizing the total pin count required.
Data Source
AI summary
A test controller implemented in an integrated circuit (IC) with partitioned scan chains provides enhanced control in performing scan tests. According to an aspect, a test controller can selectively control scan-in, scan-out and capture phases of scan tests for different scan chains of the IC to be independent. The number of pins required to interface the test controller with an external tester is less than the number of partitions that the test controller can support. According to another aspect, an IC includes a register corresponding to each partition to support transition fault (or LOS) testing. According to another aspect, an IC with partitioned scan chains includes serial to parallel and parallel to serial converters, thereby minimizing the external pins required to support scan tests.