Scan Chain Test Data Generation for Fault Localization
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Solution Overview
Problem
Current digital device testing methods for identifying blocked scan chains in integrated circuits are inefficient, often requiring additional hardware and significant computing power, and struggle to accurately locate faults without ambiguous results.
Innovation Solution
A test apparatus and method that generates reference scan chain test data by modifying input and output bit sequences to reproduce the behavior of a faulty scan chain on a faultless device, allowing for accurate failure position and type determination without additional hardware, reducing test time and improving localization accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional hardware is added to the device under test to identify blocked scan chains, then fault location accuracy is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent creates a reference scan chain test data set that copies the expected behavior of a faultless device. By comparing actual test results against this reference copy, the system can identify blocked scan chains without adding hardware to the device under test. The reference data serves as a virtual model that enables accurate fault location through software-based comparison.
Solution Approach 2:
The patent introduces an intermediary reference scan chain test data set that mediates between the device under test and the analysis process. This reference data acts as a intermediary standard against which actual test results are compared, enabling fault identification without direct hardware modification of the device under test.
2Measurement precision
If software simulation is used to perform blocked chain analysis, then fault analysis capability is improved, but computing power requirements and test time increase
Solution Approach 1:
The patent performs preliminary action by pre-calculating and storing reference scan chain test data for a faultless device before actual testing. This reference data is prepared in advance and can be quickly compared against actual test results, eliminating the need for time-consuming real-time simulations during the testing phase.
Solution Approach 2:
The patent applies partial action by focusing the simulation effort only on generating reference data for a faultless device, rather than performing exhaustive simulations for all possible fault conditions. This selective approach reduces computing requirements while maintaining effective fault analysis capability.
3Measurement precision
If complete scan chain test data is logged for analysis, then fault analysis accuracy is improved, but data processing complexity and time increase
Solution Approach 1:
The patent extracts only the essential comparison information by comparing actual test results against the reference scan chain test data. Instead of logging and processing complete test data sets, the system extracts the differential information that indicates blocked scan chains, significantly reducing data processing complexity while maintaining fault analysis accuracy.
Data Source
AI summary
A test apparatus for generating reference scan chain test data comprises a test pattern generator and an output data modifier. The test pattern generator modifies a scan chain test input bit sequence by replacing a predefined number of start bits of the scan chain test input bit sequence by a predefined start bit sequence. Further, the test pattern generator provides the modified scan chain test input bit sequence to a device under test. The output data modifier modifies a scan chain test output bit sequence received from the device under test and caused by the modified scan chain test input bit sequence. The scan chain test output bit sequence is modified by replacing a predefined number of end bits of the scan chain test output bit sequence by a predefined end bit sequence to obtain the reference scan chain test data.