Scan Chain Test Data Storage for IC Automatic Testing
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Solution Overview
Problem
Conventional IC testing methods rely heavily on external automatic test equipment (ATE), leading to high costs due to increased storage and test pin requirements, especially as the complexity of integrated circuits grows, and existing solutions like test data compression and built-in-test have limitations such as longer test times and additional storage needs.
Innovation Solution
An IC automatic test system and method that stores test data in scan chains, comprising at least one scan chain, a test controller, and a test decompressor, where test data is generated through modified connections between scan units and reconstructed by the decompressor to create test patterns for electrical testing without external ATE.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external automatic test equipment (ATE) is used to provide test data, then test coverage and reliability are improved, but test cost and storage requirements increase significantly
Solution Approach 1:
The patent merges the test data storage function into the scan chain structure itself, combining the scan chain and storage unit into a unified integrated structure. This eliminates the need for separate external storage devices and ATE, thereby reducing test cost while maintaining test coverage through the integrated test data generation and storage system
Solution Approach 2:
The scan chain is designed to generate and store its own test data internally without requiring external ATE. The test data is generated through logical operations within the scan chain units and stored in the integrated storage portion, enabling the system to serve its own testing needs autonomously and reduce external dependencies
2Device complexity
If test data compression is used to reduce ATE storage requirements, then storage cost is reduced, but additional storage space is still required
Solution Approach 1:
The storage portion is merged with the scan chain structure, using the same physical resources for both scanning and storage functions. This integration eliminates the need for separate storage devices and reduces total storage space requirements by utilizing the scan chain's inherent structure for data retention
3Device complexity
If built-in-test (BIST) is implemented to eliminate external ATE, then test cost is reduced, but test application time increases
Solution Approach 1:
Test data is pre-generated and stored in the scan chain's storage portion before the actual testing process. By preparing the test data in advance within the integrated structure, the system avoids time-consuming external data transfer while maintaining cost efficiency through the eliminated ATE dependency
4Productivity
If the number of components in IC increases to improve performance, then processing capability is improved, but test data requirements and test pin requirements increase
Solution Approach 1:
The test data generation and storage functions are merged into the scan chain structure, allowing the system to handle increased test data volumes for complex circuits without requiring proportional increases in external storage or test pins. The integrated structure efficiently manages test data internally
Solution Approach 2:
The patent utilizes the temporal dimension by generating and storing test data across multiple clock cycles within the scan chain. This approach allows comprehensive testing of increased components without requiring proportional increases in simultaneous test data volume, effectively managing data throughput for complex circuits
Data Source
AI summary
An integrated circuit (IC) automatic test system and an IC automatic test method storing test data in scan chains are revealed. The automatic test system includes at least one scan chain, a test controller and a test decompressor connected. Each scan chain consists of a storage portion with a plurality of scan units and a scan input corrector. The storage portion is for storing test data and the scan input corrector is used to adjust test patterns to be shifted into the scan chains. The test controller is for control of test flow while the test decompressor reconstructs and decompresses the test data stored in the storage portions of the scan chains to generate test patterns for the circuit under test. Thereby the IC electrical test is performed automatically and the test cost and the test cost is reduced.