Multi-Mode Scan Circuit Boundary Flip-Flop Interconnection
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Solution Overview
Problem
Current chip testing methods cannot effectively detect defects in interconnections between circuit blocks in different scan modes and combinational logic circuits, leading to reduced fault coverage due to limitations in circuit size and power consumption, and existing solutions increase circuit area and signal transmission time.
Innovation Solution
A circuit design that includes multiple scan modes with boundary scan chains, where flip-flops from one circuit block can be configured to drive and be part of another circuit block's scan chain, allowing for complete testing of interconnections and combinational logic circuits without significantly increasing circuit area, using multiplexers to control and merge scan chains for different test modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple scan modes are used to test different circuit blocks, then the circuit area and power consumption during testing are reduced, but the fault coverage is reduced because interconnections between circuit blocks in different scan modes cannot be detected
Solution Approach 1:
The patent merges scan chains from different circuit blocks by incorporating boundary scan chains that connect circuit blocks together. The boundary scan chain includes boundary cells that can be configured to connect to different circuit blocks, allowing test signals to traverse across interconnections between blocks that would otherwise be isolated in different scan modes.
Solution Approach 2:
The boundary cells in the boundary scan chain serve multiple functions: they can connect to different circuit blocks depending on configuration, they can be part of different scan modes, and they enable testing of interconnections between circuit blocks. This multi-functionality allows a single boundary scan chain to support multiple testing scenarios without requiring separate dedicated test paths for each.
2Reliability
If core wrapper is used to provide logic values to circuit block under test, then fault coverage is increased, but circuit area and signal transmission time are increased
Solution Approach 1:
Instead of using separate core wrappers for each circuit block, the patent merges the boundary scan chain functionality into the existing scan chain structure. The boundary cells are integrated into the scan chains of circuit blocks, allowing them to serve as both scan chain elements and as connectors to other circuit blocks, thereby eliminating the need for additional dedicated core wrapper structures.
Solution Approach 2:
The boundary cells serve dual purposes: they function as regular scan chain elements for testing their own circuit block, and they simultaneously serve as interface cells to connect to other circuit blocks. This multi-functionality eliminates the need for separate dedicated interface structures, reducing overall circuit area while maintaining the ability to provide logic values across interconnections.
3Ease of manufacture
If conventional electronic design automatic tools are used to implement scan chain circuits, then each circuit block can be tested independently, but interconnections between circuit blocks in different scan modes cannot be detected
Solution Approach 1:
The patent segments the scan chain implementation into regular scan chains for individual circuit blocks and a separate boundary scan chain that connects these blocks. This segmentation allows conventional tools to easily generate the regular scan chains for each block independently, while the boundary scan chain is added as a connecting layer that enables inter-block testing. The segmentation maintains ease of generation for individual blocks while adding the capability to test interconnections.
Data Source
AI summary
A circuit having multiple scan modes is disclosed. The circuit includes a first circuit block and a second circuit block. The first circuit block corresponds to a first scan mode of the multiple scan modes, and the first circuit block includes at least one first scan chain for receiving a test signal from an external automatic test equipment. The second circuit block corresponds to a second scan mode of the multiple scan modes, and the second circuit block includes at least one second scan chain for receiving another test signal from the external automatic test equipment. The second scan chain includes at least one specific flip-flop positioned in the first circuit block, and the specific flip-flop is configured to drive the second circuit block.