Scan Circuit Clock Phase Compensation for Display Brightness
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Solution Overview
Problem
Existing display technologies face challenges due to resistance-capacitance delays in signal lines, leading to uneven data charging durations and brightness variations across a display panel.
Innovation Solution
A method of driving a scan circuit involves providing time-sequentially N number of first clock signals to (k*N) stages, with each stage grouped into M groups, where the clock signals have distinct phase shifts relative to data enabling signals, and a modulation circuit converts original clock signals into these time-sequentially provided signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock signal is provided to all stages of the scan circuit, then the circuit structure is simple, but resistance-capacitance delays cause uneven data charging durations and brightness variations across the display panel
Solution Approach 1:
The scan circuit stages are divided into M groups, and a single clock signal is segmented into N different clock signals through a modulation circuit. Each group receives clock signals with different phase shifts, allowing compensation for resistance-capacitance delays without requiring separate clock signal lines for each stage, thus maintaining structural simplicity while achieving brightness uniformity
Solution Approach 2:
The modulation circuit changes the phase parameter of the clock signal for different groups of stages. By adjusting the phase shift of clock signals provided to different groups, the invention compensates for the cumulative resistance-capacitance delays, ensuring that data charging durations are equalized across all stages while maintaining a simple circuit structure
2Manufacturing precision
If clock signals are provided to compensate for resistance-capacitance delays, then brightness uniformity is improved, but the timing control of data signals becomes more complex
Solution Approach 1:
A modulation circuit is introduced as an intermediary between the single clock signal source and the multiple scan circuit stages. This intermediary converts a single clock signal into N different clock signals with appropriate phase shifts, simplifying the timing control architecture while achieving the complex goal of compensating for resistance-capacitance delays across different groups of stages
3Manufacturing precision
If different clock signals with phase shifts are provided to different groups, then data charging duration variations are reduced, but the number of clock signal variations increases
Solution Approach 1:
The modulation circuit performs multiple functions: it segments the single clock signal, adjusts phase shifts for different groups, and compensates for resistance-capacitance delays all through a single circuit component. This multi-functionality reduces the need for multiple separate clock signal generators, thereby managing clock signal variations efficiently while achieving data charging duration uniformity
Data Source
AI summary
A method of driving a scan circuit includes providing N number of first clock signals time-sequentially to (k*N) number of stages of the scan circuit, respectively. The (k*N) number of stages includes M number of groups. A respective group of the M number of groups includes one or more stages of the scan circuit. A respective first clock signal of the N number of first clock signals includes a first level component and a second level component. With respect to N number of data enabling signals, a difference between a starting point of a first level component of an n-th first clock signal and a starting point of an n-th data enabling signal of the N number of data enabling signals is equal to tm1. Values of tm1 for first clock signals provided to different groups of the M number of groups are different.