Multi-Stage Scan Circuit Layout for Stable Gate Driving
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Solution Overview
Problem
Existing display technologies face challenges in efficiently controlling image display in pixels due to limitations in gate driving circuits, particularly in the integration and performance of gate-on-array circuits within display panels.
Innovation Solution
A scan circuit design comprising multiple stages with specific subcircuits and transistors, including capacitors and transistors arranged in unique configurations to enhance control signals and improve gate driving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If gate-on-array circuits are integrated directly in the array substrate, then device integration is improved, but circuit area increases and layout complexity worsens
Solution Approach 1:
The scan circuit is divided into multiple stages, with each stage containing separate subcircuits (input subcircuit, output subcircuit, first processing subcircuit, second processing subcircuit, third processing subcircuit). This segmentation allows for modular layout optimization, reducing the overall circuit area while maintaining integration benefits.
Solution Approach 2:
Transistors are arranged in specific spatial configurations (e.g., eighth transistor on a side away from capacitors and other transistors along the first direction) to optimize the two-dimensional layout. This dimensional arrangement reduces circuit area occupation while maintaining electrical connectivity and functional performance.
2Reliability
If multiple capacitors and transistors are arranged in specific configurations, then signal transmission performance is improved, but layout complexity increases
Solution Approach 1:
Different regions of the circuit are optimized with specific component placements. For example, capacitors are positioned in specific subcircuits (first capacitor in second processing subcircuit, third capacitor in third processing subcircuit) to locally optimize signal transmission stability without requiring complex global reconfiguration.
Solution Approach 2:
The circuit design allows for flexible signal transmission paths through the multi-stage architecture, where signals can be dynamically processed through different subcircuits (input, processing, output) depending on the scanning requirements, improving adaptability without fixed complex routing.
3Stability of the object's composition
If transistors are positioned away from capacitors, then voltage stability is improved, but circuit area increases
Solution Approach 1:
The circuit is segmented into distinct functional subcircuits with capacitors and transistors separated into different regions. This segmentation maintains voltage stability by isolating capacitive elements from transistor switching activity while keeping the overall circuit area compact through efficient modular arrangement.
Data Source
AI summary
A scan circuit having a plurality of stages is provided. A respective scan unit of the scan circuit in the respective stage of the plurality of stages includes an input subcircuit, an output subcircuit, a first processing subcircuit, a second processing subcircuit, and a third processing subcircuit. The respective scan unit includes a first capacitor in the second processing subcircuit; a third capacitor in the third processing subcircuit; an eighth transistor in the first processing subcircuit; and a ninth transistor and a tenth transistor in the output subcircuit. Along the first direction, the eighth transistor is on a side of the ninth transistor and the tenth transistor away from the first capacitor, the third capacitor, and other transistors of the respective scan unit.