Scan Driving Circuit Layout for Narrow-Bezel Display Panels
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Solution Overview
Problem
Display panels face challenges in minimizing the size of the non-display region, particularly due to the large occupancy area of gate driving circuits, which hinders the reduction of the overall panel size.
Innovation Solution
The implementation of a scan driving circuit with a reduced occupancy area is achieved by using a specific transistor configuration and insulation layer arrangement, allowing for efficient integration of high-voltage and low-voltage scan signals within the non-display region, thereby minimizing the non-display area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional gate driving circuit is used in the non-display region, then the circuit can drive the pixels, but the non-display region occupies a large area
Solution Approach 1:
The patent implements a nested transistor structure where a first transistor is formed within the channel region of a second transistor. The first transistor includes a first semiconductor pattern layer, first gate electrode, and first source/drain regions, while the second transistor includes a second semiconductor pattern layer, second gate electrode, and source/drain regions that overlap with the first transistor's channel region. This nested configuration allows two transistors to share the same spatial footprint, effectively reducing the area occupied by the gate driving circuit in the non-display region.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked configuration by forming transistors in multiple layers. The first transistor is formed in a lower layer while the second transistor is formed in an upper layer, with the second gate electrode positioned above the first transistor's channel region. This vertical stacking approach utilizes the third dimension (height/thickness) to reduce the horizontal area occupation, thereby minimizing the non-display region size.
2Area of stationary object
If the non-display region is reduced to minimize panel size, then the overall panel area decreases, but the gate driving circuit occupancy becomes more constrained
Solution Approach 1:
The gate driving circuit is segmented into multiple functional blocks including start signal generation units, clock signal generation units, and scan signal output units. Each block is independently designed and formed in specific regions of the non-display area. The circuit is divided into first through fourth regions, with each region containing specific transistor configurations and signal lines. This segmentation allows for modular manufacturing and simplifies the integration process despite the reduced overall area.
Solution Approach 2:
Different regions of the gate driving circuit are designed with locally optimized transistor configurations. For example, the first transistor uses a specific semiconductor pattern layer thickness and gate electrode width in its channel region, while the second transistor has different dimensional parameters. The insulation layers are selectively positioned to provide electrical isolation where needed. These local optimizations enable efficient space utilization while maintaining manufacturability in the constrained non-display region.
Data Source
Figure 1~2
Figure 3A
Figure 3B
AI summary
A display panel includes a scan driving circuit. The scan driving circuit includes a first transistor that outputs a high-voltage of a scan signal during a turn-on period. The first transistor includes a first semiconductor pattern layer including a first input region, a first output region, and a first channel region, a first gate electrode overlapping the first channel region, a second semiconductor pattern layer including a second input region electrically connected to the first input region, a second output region electrically connected to the first output region, and a second channel region overlapping the first channel region, and a second gate electrode overlapping the second channel region, and electrically connected to the first gate electrode.