Scan-Testable Circuit Using Retention Cells for Test Control
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Solution Overview
Problem
Existing scan-based test techniques for digital logic circuits face challenges such as complex design and implementation, increased test time, and reduced scan test coverage due to limited I/O pins and reliance on dedicated test interfaces like JTAG, which complicates the test configuration and increases costs.
Innovation Solution
A scan-testable circuit design that includes additional scan cells and data retention cells configured to form a scan chain without relying on dedicated test interfaces, allowing for simplified test configuration and reduced test flow setup time through automated protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a dedicated test control interface (e.g., JTAG) is used for configuring test control registers, then test configuration capability is improved, but device complexity and cost increase
Solution Approach 1:
The patent applies universality by enabling the existing I2C functional interface to perform both its original functional communication role and an additional test configuration role. The same I/O pins and protocol infrastructure are used for both normal device operation and scan test configuration, eliminating the need for a dedicated test interface and reducing overall device complexity while maintaining full test configuration capability
2Quantity of substance
If I/O pins are multiplexed for both functional and scan purposes, then the number of required I/O pins is reduced, but test time increases due to protocol decoding complexity
Solution Approach 1:
The patent applies self-service by having the scan chain cells automatically detect and adapt to the I2C protocol format for test configuration data. Instead of requiring external protocol decoding logic, the scan cells themselves are configured to recognize I2C address and data formats, enabling direct loading of test control register values from the I2C interface without additional processing delays
3Adaptability or versatility
If functional and scan configuration of I/O pins are interleaved, then interface utilization is improved, but design complexity and implementation difficulty increase
Solution Approach 1:
The patent applies dynamics by implementing a reconfigurable I/O pin system that can dynamically switch between functional mode and scan test mode based on the active I2C transaction type. The same physical pins and underlying logic are flexibly allocated to different purposes through protocol-based control, allowing high interface utilization while maintaining relatively simple design through unified infrastructure
4Adaptability or versatility
If a full reset or power cycling is performed to alternate between functional and scan modes, then mode switching capability is improved, but test time significantly increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring the scan chain cells to recognize I2C protocol formats and pre-establishing the data paths between the I2C interface and test control registers. This preliminary setup allows rapid mode transitions through simple protocol interpretation rather than requiring full system reset, enabling fast switching between functional and scan modes while maintaining full mode switching capability
Data Source
AI summary
A scan-testable integrated circuit includes a logic circuit configured to receive test mode control signals, a signal interface configured to receive scan-in, scan enable and scan clock signals, and produce a scan-out signal, and a scan register including a plurality of scan cells coupled to the signal interface to receive the scan enable and scan clock signals. Additional scan cells are coupled to the signal interface, and configured to receive and propagate the scan-in signal when the scan enable signal is asserted. Data retention cells are coupled to respective ones of the additional scan cells and to the logic circuit, and configured to provide as output the values stored in the respective additional scan cells to produce the test mode control signals when the scan enable signal is de-asserted, and configured to prevent the test mode control signals from changing value when the scan enable signal is asserted.