Scan Driving Circuit With Dynamic Discharge Voltage for Low-Power Self-Scan
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Solution Overview
Problem
Existing display devices face challenges in reducing power consumption while maintaining efficient image display performance.
Innovation Solution
A scan driving circuit is designed with an input transistor, output transistor, and discharge control transistor, utilizing different voltage levels and clock signal configurations in address and self-scan periods to optimize power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the discharge voltage is maintained at a high voltage level throughout the entire frame period, then the scan signal can be quickly discharged during the address period, but power consumption increases during the self-scan period
Solution Approach 1:
The discharge control transistor dynamically changes the discharge voltage level based on the operating period. During the address period, the discharge voltage is at a high voltage level to enable quick discharge of the scan signal. During the self-scan period, the discharge voltage is lowered to a low voltage level to reduce power consumption while maintaining the scan signal at a low voltage level.
Solution Approach 2:
The patent changes the voltage parameter of the discharge control transistor from a constant high voltage to a variable voltage that switches between high and low levels. This parameter change allows the system to optimize between discharge speed and power consumption by adjusting the discharge voltage according to the operational requirements of different periods.
2Use of energy by moving object
If transistors are switched off during the self-scan period to reduce power consumption, then power draw decreases, but the scan signal cannot be quickly activated when needed
Solution Approach 1:
The circuit prepares for quick activation by maintaining the output transistor in a turn-on state during the self-scan period through the low discharge voltage, while keeping the scan signal itself at a low voltage level. This preliminary preparation ensures that when activation is needed, the transistor is already ready to quickly switch the scan signal to a high voltage level without delay.
3Adaptability or versatility
If the clock signal continuously switches during the self-scan period, then the circuit remains responsive, but power consumption increases
Solution Approach 1:
The clock signal operates periodically, switching during the address period to enable circuit responsiveness and signal processing, then stopping or maintaining a constant level during the self-scan period to reduce power consumption. This periodic operation pattern allows the circuit to be responsive when needed while conserving energy during periods of lower activity.
Data Source
AI summary
Disclosed is a scan driving circuit that includes an input transistor, an output transistor, and a discharge control transistor. The input transistor is connected between an input terminal, that receives a start signal, and a first node. The input transistor includes a gate electrode connected to a clock terminal. The output transistor is connected between an output terminal, that outputs a scan signal, and a first voltage terminal. The output transistor includes a gate electrode connected to the first node. The discharge control transistor is connected between the first node and a second voltage terminal, and includes a gate electrode connected to the second voltage terminal. Each frame of a second plurality of frames of the start signal includes an address period and a self-scan period. In the address period, a discharge voltage provided to the second voltage terminal is a high voltage. In the self-scan period, a voltage level of the discharge voltage is lower than a voltage level of the high voltage.