Sequential Scan Circuit With Redundant Feedback Against SET Errors
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Solution Overview
Problem
Integrated circuits face errors due to single event transients (SETs), which can cause temporary voltage disturbances leading to incorrect output changes, and existing solutions do not effectively prevent malfunctions without degrading performance.
Innovation Solution
A sequential circuit design incorporating a data input terminal, a first data path transmitting data based on both a normal and a delayed clock signal, and a redundant feedback loop that stores data only when the data values are equal, using a clock generator to generate these clock signals and ensure robustness against SETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a redundant feedback loop is added to prevent SET errors, then reliability is improved, but device complexity increases
Solution Approach 1:
The redundant feedback loop is configured to proactively detect and correct SET errors before they propagate through the circuit. By continuously monitoring data through the feedback path and comparing it with delayed data, the circuit performs preliminary error detection and correction, preventing malfunction before it occurs.
Solution Approach 2:
The patent creates a redundant copy of the data path through the feedback loop, which includes a delayed version of the data. This copied data path allows for comparison and verification without altering the primary data flow, enabling error detection while maintaining the original circuit functionality.
2Reliability
If data is stored in the redundant feedback loop continuously, then reliability against SETs is improved, but loss of time increases due to additional processing
Solution Approach 1:
The redundant feedback loop stores data periodically based on clock signals rather than continuously. The circuit uses clocked operation to update the feedback data at specific intervals, which maintains data stability for SET protection while avoiding continuous processing delays. This periodic updating ensures that data is refreshed only when necessary.
Solution Approach 2:
The patent employs a delayed data path that creates temporary, short-lived copies of data for comparison purposes. These delayed data versions are transient and discarded after comparison, allowing the circuit to verify data integrity without permanently storing multiple data versions, thus minimizing time loss.
3Reliability
If a delayed clock signal is used in the first data path, then robustness against SETs is improved, but speed decreases due to signal delay
Solution Approach 1:
The patent introduces a time dimension by using delayed clock signals to create multiple temporal phases of data transmission. The first data path operates with a delayed clock signal for enhanced SET protection, while the feedback loop operates with undelayed or differently phased clock signals. This multi-dimensional temporal approach allows error protection without uniformly slowing down the entire circuit.
Solution Approach 2:
The delayed clock signal is applied selectively to specific portions of the circuit (the first data path) rather than the entire circuit. This localized application of delay ensures that only the critical path requiring SET protection experiences speed reduction, while other parts of the circuit maintain their original timing and speed characteristics.
Data Source
AI summary
A sequential circuit includes a data input terminal, a data path, and a redundant feedback loop. The data input terminal receives input data. The data path is connected to the data input terminal and transmits the input data to a data output terminal based on a first clock signal and a second clock signal. The redundant feedback loop is connected to the first data path and stores first data based on at least one of the first or second clock signals when the first data is equal to second data. The first data corresponds to the input data. The second clock signal is a delayed signal of the first clock signal. The second data is delayed data of the first data.