Scan Circuit Layout for Stable Display Gate Driving Signals
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Solution Overview
Problem
Existing scan circuits in display technology suffer from output signal fluctuations, leading to jittering of gate driving signals that adversely affect display quality.
Innovation Solution
The scan circuit incorporates specific transistor and capacitor layouts, including a first capacitor with a unique electrode structure and strategically positioned transistors, to stabilize voltage levels and reduce coupling fluctuations, thereby enhancing signal stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional scan circuit layouts are used, then device complexity is reduced, but output signal fluctuations increase leading to jittering gate driving signals
Solution Approach 1:
The scan circuit is divided into multiple stages with each stage containing specific transistor and capacitor configurations. The circuit segments include input subcircuits, processing subcircuits, and output subcircuits, where each segment performs a specific function in signal processing and transmission, thereby reducing overall signal fluctuations through distributed stabilization.
Solution Approach 2:
Different regions of the circuit are designed with specific transistor types and capacitor configurations tailored to local signal processing needs. For example, input transistors have different characteristics than output transistors, and capacitors are strategically placed at specific nodes to stabilize voltage levels where needed most, optimizing signal stability without uniformly increasing complexity throughout the entire circuit.
2Reliability
If transistor and capacitor layouts are optimized for stability, then output signal fluctuations are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The circuit design utilizes multi-layer substrate structures where transistors and capacitors are arranged in different vertical layers. Connecting lines traverse between layers to connect circuit elements, allowing optimized signal paths and stabilization nodes without requiring excessively tight lateral spacing, thereby reducing manufacturing precision requirements while maintaining signal stability.
3Area of stationary object
If compact circuit design is used, then area is reduced, but coupling fluctuations between adjacent components increase
Solution Approach 1:
Capacitors are positioned to overlap with transistor regions in the vertical dimension, with capacitor electrodes nested over or under transistor active areas. This nesting arrangement allows both components to occupy the same footprint area without increasing lateral space requirements, while the vertical separation prevents harmful electrical coupling between the nested components.
4Adaptability or versatility
If connecting lines are routed to cross over capacitor electrodes, then layout flexibility is improved, but parasitic capacitance increases
Solution Approach 1:
Connecting lines are routed in different vertical layers relative to capacitor electrodes. When a connecting line needs to cross over a capacitor electrode in the planar view, the line is placed in an upper or lower conductive layer, allowing the crossing without creating significant parasitic capacitance. This multi-layer routing provides layout flexibility while minimizing harmful electrical coupling.
Data Source
AI summary
A scan circuit includes a plurality of stages. A respective stage of the scan circuit includes a second processing subcircuit, which includes a first capacitor, a sixth transistor, and a seventh transistor; and an input subcircuit including a first transistor, and an input signal line configured to provide an input signal to the first transistor. The respective stage of the scan circuit further includes a sixth connecting line connecting a first electrode of the seventh transistor, a second electrode of the sixth transistor, and a second capacitor electrode of the first capacitor together. The sixth connecting line crosses over both the first capacitor electrode and the second capacitor electrode of the first capacitor. A shortest distance between an active layer of the seventh transistor and the input signal line is less than a shortest distance between an active layer of the sixth transistor and the input signal line.