Scan Driving Circuit Layout for Stable Low-Area Scan Signals
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Solution Overview
Problem
Existing scan driving circuits in electronic devices are inefficient in minimizing the circuit area and optimizing the operation of scan lines, leading to increased non-display areas in devices.
Innovation Solution
A scan driving circuit design that includes a switching circuit to deliver specific voltage levels to nodes in response to clock and carry signals, utilizing transistors of different types and a capacitor to stabilize output signals, minimizing the number of transistors and capacitors, and optimizing the scan signal generation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional scan driving circuit designs are used, then the circuit can operate scan lines, but the circuit area is increased leading to larger non-display areas
Solution Approach 1:
The patent merges the functions of multiple transistors into a compact configuration where the first and second output transistors share common control nodes (first and second nodes) with the switching circuit. This integration reduces the overall circuit area while maintaining the stability of scan signal generation through optimized voltage delivery mechanisms.
Solution Approach 2:
The switching circuit is designed to deliver different voltage levels (first voltage, second voltage, third voltage) to different nodes based on clock signals and carry signals. This multi-functional switching circuit replaces what would traditionally require separate dedicated circuits for each voltage level, reducing total circuit area while ensuring reliable operation.
2Area of stationary object
If the number of transistors is reduced to minimize circuit area, then device compactness is improved, but the complexity of optimizing transistor configuration increases
Solution Approach 1:
The circuit is segmented into functional blocks: a switching circuit with transistors (first through fifth transistors) that controls voltage delivery, and output transistors (first and second output transistors) that generate scan signals. This segmentation allows each block to be optimized independently, reducing overall complexity while minimizing area.
Solution Approach 2:
The patent utilizes different voltage parameters (first voltage, second voltage, third voltage) applied at different times controlled by clock signals and carry signals. By changing voltage parameters dynamically rather than using fixed configurations, the circuit achieves compactness without sacrificing operational reliability.
3Use of energy by moving object
If voltage levels are optimized to improve scan signal efficiency, then power consumption is reduced, but the precision of voltage control requirements increase
Solution Approach 1:
The switching circuit operates periodically based on clock signals (first clock signal, second clock signal) and carry signals, delivering different voltage levels at different time periods. This periodic voltage delivery optimizes power consumption by applying voltage only when needed, while the rhythmic nature of clock-based control simplifies voltage precision requirements compared to continuous control.
Solution Approach 2:
The circuit uses its own internal clock signals and carry signals to automatically control the switching of voltage levels without requiring external precision voltage control mechanisms. The transistors self-regulate their operation based on the timing signals, reducing both power consumption and the precision requirements for external voltage control.
Data Source
AI summary
A scan driving circuit includes: a switching circuit configured to deliver a third voltage to a first node in response to a carry signal and a first clock signal and to deliver the third voltage to a second node in response to the first clock signal; a first output transistor connected between a first voltage terminal and an output terminal, and configured to operate in response to a second signal of the second node, wherein the first voltage terminal receives a first voltage; and a second output transistor connected between the output terminal and a second clock terminal, and configured to operate in response to a first signal of the first node.