Scan Clock Buffer Grouping to Reduce Chip Voltage Droop
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Solution Overview
Problem
Existing VLSI circuit devices face challenges in testability due to high power consumption and voltage drooping during scan operations, which affect test time and wafer testing efficiency.
Innovation Solution
Implementing a method that uses at least two local clock buffers triggered by a base clock signal, separates scan data launch and capture clocks with variable time delays, and categorizes latches into dedicated buffer group categories to distribute data launches evenly over capture cycles, reducing voltage drooping and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all latches launch their data at the same clock pulse during scan, then test operation is simple and fast, but voltage drooping and power consumption increase
Solution Approach 1:
The patent segments the simultaneous data launch operation into multiple staged launches. By dividing the latch population into different groups that launch data at different time intervals rather than all at once, the patent reduces peak power consumption while maintaining test throughput. This segmentation of the scanning process allows voltage drooping to be minimized through distributed timing.
Solution Approach 2:
The patent implements periodic action by using multiple scan clocks with different phases or timings. Instead of a single simultaneous launch, the system uses sequential clock signals to trigger different latch groups at periodic intervals, spreading out the power demand over time while maintaining the scanning function.
2Loss of time
If all latches launch data simultaneously, then test time is minimized, but voltage drooping increases affecting test accuracy
Solution Approach 1:
The patent segments the simultaneous data launch operation into multiple staged launches. By dividing the latch population into different groups that launch data at different time intervals rather than all at once, the patent reduces peak power consumption while maintaining test throughput. This segmentation of the scanning process allows voltage drooping to be minimized through distributed timing.
Solution Approach 2:
The patent applies preliminary action by pre-calculating and pre-arranging the scan chain reordering before the actual scanning begins. The system determines optimal launch timing for different latch groups in advance, allowing the scanning process to proceed efficiently without voltage drooping issues during execution.
3Loss of energy
If scan chain is reordered to minimize peak power dissipation, then power consumption decreases, but device complexity increases
Solution Approach 1:
The patent applies dynamics by making the scan chain configuration adaptable rather than fixed. The system dynamically reorders the scan chain based on power consumption constraints and can adjust the timing and sequencing of data launches in real-time during testing, allowing the same hardware to operate under different power scenarios without requiring complex permanent reconfiguration.
Solution Approach 2:
The patent changes operational parameters such as clock timing, scan chain ordering, and launch sequencing to achieve lower power dissipation. By adjusting these parameters rather than fundamentally redesigning the hardware, the system reduces power consumption while keeping the physical device structure relatively simple.
Data Source
AI summary
Disclosed are techniques for reducing voltage drooping in a microelectronic chip, including separating a scan data launch clock from a capture clock with a variable time delay depending on a delay of a succeeding scan path of the latches, where the scan data launch clock and the capture clock are based on a base clock signal. The techniques further include analyzing and categorizing the latches against the time delay into dedicated buffer group categories. The techniques further include assigning the at least two local clock buffers to the latches within the dedicated buffer group categories.