Scan Clock Circuit for Parallel At-Speed Testing
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Solution Overview
Problem
Current scan testing methods face challenges in generating at-speed pulses for high-frequency clock domains due to parasitics limiting signal frequency through I/O pads, and existing solutions are complex and require additional hardware or large frequency dividers, making them inefficient for parallel testing of low- and high-frequency domains.
Innovation Solution
A method and circuit that generate parallel scan clock signals for both low- and high-frequency domains using a single ATE clock and scan enable signal, allowing for at-speed testing in launch-on-shift and launch-on-capture modes, without the need for additional on-chip clock controllers or large frequency dividers, thereby reducing test time and silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single ATE clock is used to generate scan clock signals for both low- and high-frequency domains, then test time is reduced and productivity is improved, but generating at-speed pulses for high-frequency domains becomes difficult due to parasitics limiting signal frequency through I/O pads
Solution Approach 1:
The patent divides the scan testing into separate low-frequency and high-frequency domains, each with dedicated scan chains. The clock control circuit segments the single ATE clock signal to generate appropriate scan clock signals for each domain, allowing parallel testing without frequency conflicts
Solution Approach 2:
The patent introduces an on-chip clock controller as an intermediary between the ATE and the scan chains. This controller generates internal clock signals and at-speed pulses that overcome the frequency limitations of external I/O pads, enabling high-frequency domain testing while maintaining parallel operation
2Reliability
If additional on-chip clock controllers or large frequency dividers are used to generate parallel scan clock signals, then at-speed testing capability is improved, but device complexity and silicon area increase
Solution Approach 1:
The patent designs a unified clock control circuit that performs multiple functions: generating scan clock signals for low-frequency domains, generating at-speed pulses for high-frequency domains, and coordinating parallel testing operations. This multi-functional approach eliminates the need for separate clock controllers and frequency dividers
Solution Approach 2:
The patent merges the clock control functionality for both low- and high-frequency domains into a single integrated circuit block. By combining these functions, the patent reduces the number of separate hardware components needed while maintaining full at-speed testing capability across both domains
Data Source
Figure 1A~1B
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AI summary
In an embodiment, a method for performing scan testing includes: generating first (CLKscan_lf) and second (CLKscan_hf) scan clock signals; providing the first and second scan clock signals to first (524) and second (514) scan chains, respectively, where the first and second scan clock signals includes respective first shift pulses when a scan enable signal (scan_en) is asserted, and respective first capture pulses when the scan enable signal (scan_en) is deasserted, where the first shift pulse of the first (CLKscan_lf) and second (CLKscan_hf) scan clock signals correspond to a first clock pulse of a first clock signal (CLKslow), where the first capture pulse of the first scan clock signal (CLKscan_lf) corresponds to a second clock pulse of the first clock signal (CLKslow), and where the first capture pulse of the second scan clock signal (CLKscan_hf) corresponds to a first clock pulse of a second clock signal (CLKfast) different from the first clock signal (CLKslow).