Scan Clock Control Circuit for Semiconductor Noise Reduction
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Solution Overview
Problem
In semiconductor device scan tests, the simultaneous switching of all scan flip-flops generates significant switching noise, which can be mitigated by reducing the number of simultaneously transitioning scan data, but this approach increases test time as the number of scan patterns increases.
Innovation Solution
The semiconductor device incorporates a shift clock control circuit that generates non-inverted and inverted scan clock signals, controlling the ratio of simultaneously switched scan flip-flops to distribute switching noise across both rising and falling edges of the scan clock signal, thereby reducing peak noise without extending test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all scan flip-flops are simultaneously switched during scan shift operation, then scan test can be performed efficiently, but switching noise becomes large
Solution Approach 1:
The patent divides the scan flip-flops into multiple groups and controls them to switch at different times within the same scan shift operation. By segmenting the simultaneous switching into staged switching across multiple clock edges, the patent reduces switching noise while maintaining scan test efficiency without increasing test time.
Solution Approach 2:
The patent utilizes periodic scan clock signals with different phases to control the switching of scan flip-flops in groups. By using periodic action with phase differences, the patent distributes switching noise across multiple time periods and reduces peak noise levels while maintaining efficient scan test operation.
2Object-generated harmful factors
If the number of scan data transitioning simultaneously is decreased, then switching noise is reduced, but test time period increases
Solution Approach 1:
The patent segments the scan flip-flops into groups that switch at different clock edges (rising and falling edges). This segmentation allows reducing simultaneous switching noise while completing all scan patterns within the same test time period, avoiding the time penalty of sequential switching of all flip-flops.
Solution Approach 2:
The patent dynamically controls the switching timing of scan flip-flop groups based on the scan clock signal phases. By making the switching timing dynamic and adaptable to the clock edges, the patent optimizes noise reduction without sacrificing test time efficiency.
Data Source
AI summary
A semiconductor device of the embodiment includes a plurality of scan chains, a shift clock control circuit, and a shift clock generation circuit. The plurality of scan chains each include a plurality of scan flip-flops. The shift clock control circuit outputs, to each of the plurality of scan chains, a control signal that non-inverts or inverts a scan clock signal. The shift clock generation circuit is provided to each of the plurality of scan flip-flops and generates a non-inverted scan clock signal or an inverted scan clock signal based on the control signal, the non-inverted scan clock signal being obtained by non-inverting the scan clock signal, the inverted scan clock signal being obtained by inverting the scan clock signal.