Scan Clock Domain Allocation for IC Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional scan clock domain allocation methods in integrated circuit testing are inefficient, leading to increased area and power consumption due to timing violations, particularly when grouping asynchronous or functionally unrelated clock domains, requiring repetitive processes and significant resources.
Innovation Solution
A method utilizing a circuit netlist file and timing constraints file to generate a clock domain report, which groups and allocates function clock domains into a reduced number of scan clock domains, optimizing the allocation process by analyzing crossing paths and user configuration settings to minimize timing violations and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple function clock domains are grouped into scan clock domains to share the same scan clock, then the number of scan clocks is reduced and pin usage is optimized, but timing violations increase significantly when grouping asynchronous or functionally unrelated clock domains
Solution Approach 1:
The patent performs preliminary analysis of clock domain characteristics (asynchronous vs synchronous, functional relationships) before grouping, and pre-establishes scan clock allocation plans that account for potential timing violations. This allows the system to prepare appropriate scanning strategies in advance, such as using multiple scan clocks with staggered phases or adjusting scan sequences, thereby reducing timing violations while maintaining reduced pin usage.
2Ease of manufacture
If conventional scan clock domain allocation methods are used, then the allocation process is simple, but the process requires repetitive iterations after clock tree synthesis and consumes significant time and resources
Solution Approach 1:
The patent performs comprehensive analysis of clock domain characteristics, crossing paths, and timing relationships before the allocation process begins. By pre-calculating optimal groupings and preparing allocation plans in advance, the system eliminates the need for multiple iterative corrections after clock tree synthesis, significantly reducing time and resource consumption while maintaining allocation effectiveness.
Solution Approach 2:
The patent incorporates feedback mechanisms that continuously monitor timing violations and allocation effectiveness during the scanning process. When timing issues are detected, the system automatically adjusts scan clock assignments, modifies scanning sequences, or regroups clock domains to resolve violations, thereby eliminating the need for manual iterative corrections and reducing overall processing time.
3Device complexity
If asynchronous clock domains with large false paths are grouped together, then the number of scan clock domains is reduced, but the area and power consumption increase to fix timing violations
Solution Approach 1:
The patent performs preliminary identification and classification of clock domain characteristics, particularly analyzing false paths and timing relationships before grouping. By pre-planning scan clock allocations that account for asynchronous characteristics and false path lengths, the system can avoid creating timing-critical groupings that would require additional area and power for correction, thereby reducing overall power consumption while maintaining efficient clock domain reduction.
Data Source
AI summary
A method for deciding a scan clock domain allocation of an integrated circuit includes: utilizing a circuit netlist file and a timing constraints file of the integrated circuit to find out the amount of crossing paths between any two function clock domains of a plurality of function clock domains, and generate a clock domain report file; and grouping the plurality of function clock domains and allocating the plurality of function clock domains after being grouped into a plurality of scan clock domains according to the clock domain report file.