Scan Test Clock Encoder for Multi-Clock Domain Capture
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Solution Overview
Problem
Scan-based testing of integrated circuits with portions operating in different clock domains faces challenges such as setup/hold violations and erroneous data capture due to clock skew, which existing methods attempt to address with additional pins or buffers, but these solutions increase implementation area and power consumption or reduce fault coverage.
Innovation Solution
An encoder is implemented to manage capture pulses across clock domains, ensuring that only one domain receives the capture pulse during scan testing, thereby avoiding setup/hold violations and reducing the need for additional pins, while maintaining test quality and fault coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional pins or buffers are used to address setup/hold violations in multi-clock domain testing, then testing reliability is improved, but implementation area and power consumption increase
Solution Approach 1:
The integrated circuit is divided into multiple clock domains, each with its own capture pulse generation logic. The encoder segments the capture pulse distribution so that only one clock domain receives the capture pulse at a time, eliminating the need for additional buffers or pins while maintaining testing reliability across all domains.
2Reliability
If additional pins or buffers are used to address setup/hold violations in multi-clock domain testing, then testing reliability is improved, but power consumption increases
Solution Approach 1:
The testing system is segmented into independent clock domain units, each capable of autonomous capture pulse generation through the encoder. This eliminates the need for power-hungry additional buffers and pins, as each domain uses its own localized logic to ensure reliable capture without external assistance.
3Device complexity
If a single test clock is used for all portions, then the number of pins required is reduced, but timing violations may occur across different clock domains
Solution Approach 1:
The system dynamically adapts the single test clock signal through the encoder, which selectively enables capture pulses in different clock domains based on timing requirements. This dynamic control allows one clock input to serve multiple domains with different timing characteristics, reducing pin count while maintaining timing accuracy through intelligent signal distribution.
4Reliability
If capture pulses are forwarded to all clock domains simultaneously, then testing coverage is improved, but setup/hold violations and erroneous data capture occur
Solution Approach 1:
The encoder implements periodic action by sequentially enabling capture pulses for different clock domains in alternating cycles. This periodic alternation ensures that each domain receives capture pulses at appropriate intervals, maintaining full testing coverage across all domains while preventing setup/hold violations that would occur with simultaneous pulse distribution.
Data Source
AI summary
An integrated circuit containing an encoder which avoids setup/hold violation in a memory element of one clock domain, when receiving data from another memory element of another clock domain during a scan based testing of an integrated circuit. In an embodiment, the encoder receives a test clock, including a capture pulse during a capture mode of the scan test, but forwards the capture pulse only to one of the clock domains and blocking the capture pulse to other clock domains. As a result, erroneous captures in the memory element receiving data from another clock domain is avoided without the need of closing timing on paths which are not functionally exercised.