Scan Clock Gating for Multi-Block Stuck-at Fault Capture
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Solution Overview
Problem
Existing digital circuit designs face issues with hold-time violations during scan tests between block circuits due to limited scan clocks, leading to incomplete test coverage when testing asynchronous interfaces.
Innovation Solution
A scan clock gating controller that generates multiple one-hot control signals to enable and disable final scan clocks for each block circuit independently, ensuring only one clock is active during the capture phase, thereby preventing simultaneous switching and resolving hold-time violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single scan clock is directly transmitted to multiple block circuits, then the chip can perform scan tests with limited pins, but hold-time violation occurs during capture phase causing test failure
Solution Approach 1:
The patent divides a single scan clock signal into multiple separate scan clock signals, with each block circuit receiving its own dedicated scan clock. This segmentation allows independent control of clock edges for each block, enabling successful capture phase operations without hold-time violations while maintaining scan test functionality across all blocks.
2Reliability
If multiple scan clocks are provided to multiple block circuits, then hold-time violation is avoided, but the number of pins required increases
Solution Approach 1:
The patent merges the functionality of multiple external scan clock inputs into a single external scan clock input. By using internal clock gating circuits and control logic, the system generates multiple independent scan clock signals from one external source, thereby avoiding hold-time violations without increasing the pin count.
Solution Approach 2:
The patent introduces intermediate clock gating circuits and control logic as mediators between the single external scan clock input and the multiple block circuits. These intermediaries generate the necessary multiple scan clock signals with appropriate phase relationships, eliminating the need for multiple external pin connections while ensuring reliable testing.
3Measurement precision
If scan clocks are enabled for all block circuits simultaneously during capture phase, then testing coverage is maximized, but hold-time violation causes test failure
Solution Approach 1:
The patent implements dynamic control of scan clock signals using clock gating circuits that can independently enable or disable clocks for different blocks based on test mode signals. During capture phase, the system dynamically configures which blocks receive active clocks, allowing full test coverage of enabled blocks while preventing hold-time violations through controlled clock distribution.
Data Source
AI summary
A scan clock gating controller and a method for performing a stuck-at fault test among multiple block circuits are provided. The scan clock gating controller includes a decoder and multiple clock gating circuits. The decoder is configured to generate multiple one-hot control signals according to a selection signal. The multiple clock gating circuits are configured to generate multiple final scan clocks to the multiple block circuits according to the multiple one-hot control signals, a scan enable signal and an initial scan clock. When the scan enable signal has a first logic value, the multiple clock gating circuits enable the multiple final scan clocks, respectively. When the scan enable signal has a second logic value, the multiple clock gating circuits control whether to enable the multiple final scan clocks according to the multiple one-hot control signals, respectively.