Scan Clock Suppression for Asynchronous IP Core Testing
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Solution Overview
Problem
The increasing complexity and size of integrated circuits (ICs) lead to higher costs and complexities in scan testing, with traditional scan test methods being inefficient due to asynchronous scan control signals and the need for extensive pipelining and latency equalization, resulting in prolonged testing times and resource overhead.
Innovation Solution
The integration of wave shaping circuits within ICs that detect trigger events on scan control signals to selectively suppress the scan clock for a specific number of clock cycles, synchronizing scan data and control signals and reducing the need for pipeline equalization and dummy clock cycles, thereby reducing testing time and hardware overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional scan test methods are used with asynchronous scan control signals, then scan testing can be performed on ICs, but testing time is prolonged and hardware overhead increases due to the need for extensive pipelining and latency equalization
Solution Approach 1:
The patent implements dynamic scan clock suppression controlled by wave shaping circuits that respond to trigger events on scan control signals. The scan clock is selectively suppressed for a programmable number of clock cycles based on actual signal arrival timing, transforming the static asynchronous approach into a dynamic synchronized approach that adapts to varying signal propagation delays without requiring extensive fixed pipelining
Solution Approach 2:
The patent changes the timing parameters of the scan clock signal by suppressing it for specific durations based on detected trigger events. This parameter modification allows the system to compensate for asynchronous signal arrivals and pipeline latency variations dynamically, eliminating the need for conservative fixed pipelining and reducing overall testing time
2Reliability
If extensive pipelining and latency equalization are implemented to handle asynchronous scan control signals, then scan testing can be performed, but hardware overhead and device complexity increase
Solution Approach 1:
The patent extracts the latency equalization function from the traditional extensive pipelining approach and implements it through compact wave shaping circuits that generate clock suppression signals. This extraction removes the need for multiple pipeline stages and complex latency equalization logic, significantly reducing hardware overhead while maintaining the necessary timing synchronization
Solution Approach 2:
The wave shaping circuit acts as an intermediary between the asynchronous scan control signals and the scan clock. It detects trigger events on control signals and mediates the timing relationship by suppressing the scan clock appropriately, eliminating the need for complex direct synchronization logic and reducing overall circuit complexity
3Adaptability or versatility
If synchronous scanning is implemented across multiple IP cores, then test patterns can be reused without retargeting, but scan control signals must be synchronized across different pipeline stages
Solution Approach 1:
The patent segments the synchronization function into individual wave shaping circuits associated with each IP core instance. Each circuit independently handles the timing synchronization for its associated core by detecting local trigger events and suppressing the scan clock accordingly. This segmentation allows test patterns to be reused across multiple cores without retargeting while distributing the synchronization complexity across independent, identical circuit modules
4Ease of operation
If asynchronous scan control signals are used without suppression, then simpler control logic is needed, but dummy clock cycles are required resulting in prolonged testing time
Solution Approach 1:
The patent maintains continuous useful action by suppressing the scan clock only during the specific periods when asynchronous control signals are propagating through the pipelines. Rather than using dummy clock cycles that perform no useful function, the system continuously advances testing during non-suppression periods while pausing only when necessary, eliminating wasted time without complicating the control logic
Data Source
AI summary
An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.