Scan Compression Architecture with Reconfigurable Data Selectors
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Solution Overview
Problem
Existing scan compression testing techniques face challenges with low compression ratios and significant test coverage loss due to high horizontal dependencies and pattern inflation, leading to increased test time and data volume in integrated circuits.
Innovation Solution
A scan compression architecture with reconfigurable scan paths, utilizing initial and additional data selectors controlled by a mode select input to implement different load and unload value dependencies, allowing for two modes of scan compression and reconfiguring the order of IC elements within scan paths to reduce horizontal dependencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high compression ratios (60-80× or beyond) are implemented in scan compression testing, then test data volume is reduced, but test coverage quality deteriorates with coverage drop greater than 1% and real compression as low as 3-5× due to pattern inflation
Solution Approach 1:
The scan compression architecture is segmented into multiple independent scan chains rather than treating the entire scan path as a single unit. Each scan chain can be independently configured with data selectors, allowing the system to divide the compression task into manageable segments that maintain coverage quality while achieving overall high compression ratios.
Solution Approach 2:
The scan compression architecture employs dynamic reconfiguration capabilities through data selectors that can change the order of IC elements within scan paths based on test requirements. This dynamic adjustment allows the system to optimize between compression ratio and coverage quality for different test scenarios, preventing the static trade-off between compression and coverage.
2Reliability
If reconfigurable scan paths with additional data selectors are implemented, then horizontal dependencies are reduced and test coverage is enhanced, but device complexity increases
Solution Approach 1:
The data selectors in the scan compression architecture are designed with multi-functionality, serving both as compression elements and as reconfiguration switches. This universal component performs multiple functions: compressing test data, reordering scan path elements, and controlling scan chain configuration, thereby reducing the need for separate dedicated components and mitigating the complexity increase.
3Loss of time
If scan compression is applied to reduce test data volume, then test time is reduced, but compression efficiency deteriorates due to pattern inflation resulting in real compression of only 3-5×
Solution Approach 1:
The architecture changes the parameters of scan path configuration by allowing dynamic reordering of IC elements within scan paths. This parameter change enables the system to optimize the arrangement of scan elements to minimize pattern inflation and maximize real compression ratios, thereby improving compression efficiency while maintaining reduced test time.
Data Source
AI summary
An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements (e.g. flip-flops) coupled together to define a plurality of scan paths. The block of IC elements includes an initial data selector at an initial position of each of the scan paths, and an additional data selector downstream within at least one of the scan paths and configured to reconfigure an order of the IC elements within the at least one scan path. Compression logic is coupled between the block of IC elements and a test access output.