Scan-Based Debugging for IC Flip-Flop State Access
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Solution Overview
Problem
Current silicon diagnosis methods for integrated circuits are limited in their ability to efficiently access and analyze the internal signal states of flip-flops across different clock and voltage domains, requiring separate tools and impacting the original design with timing and area considerations.
Innovation Solution
An integrated circuit with a scan-based debugging method that utilizes an embedded in-circuit emulator to freeze operations, dump states of flip-flops using existing hardware, and transfer these states to a computer via a test interface, allowing for software debugging with minimal timing or area impact, and enabling access to flip-flop states across different clock and voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If dedicated debug registers and test wrappers are used to access internal signal states, then debugging capability is improved, but device complexity and area increase
Solution Approach 1:
The scan chain is designed to serve dual purposes: normal operational data storage/transfer and debugging state access. By reusing the existing scan chain infrastructure for both functional operations and diagnostic purposes, the patent eliminates the need for separate dedicated debug registers and test wrappers, thereby improving debugging capability without increasing device complexity or area
Solution Approach 2:
The system uses its own existing hardware resources (scan chains, on-chip memory, test interface) to perform debugging functions. The scan chain dumps states of flip-flops into on-chip memory, which is then accessed through the existing test interface, allowing the circuit to debug itself without requiring external dedicated debugging hardware
2Measurement precision
If separate debugging tools are used for different clock and voltage domains, then measurement precision is improved, but device complexity and ease of operation worsen
Solution Approach 1:
The scan chain is designed to universally access flip-flops across different clock and voltage domains through a single unified interface. The same scan chain infrastructure that operates normally is repurposed to dump states from any domain, eliminating the need for separate debugging tools for each domain while maintaining precise access to all signal states
Solution Approach 2:
The debugging system is segmented into functional components that work independently: the scan chain captures states, on-chip memory stores them, and the test interface transfers them externally. This segmentation allows precise access to states in any clock or voltage domain without requiring complex integrated debugging tools for each domain
3Ease of manufacture
If scan chains are used for debugging, then ease of manufacture and device complexity are improved, but timing constraints may worsen
Solution Approach 1:
The scan chain operates in periodic cycles: during normal operation, it performs functional data storage and transfer; during debugging mode, it dumps states into on-chip memory. This periodic switching between operational modes allows the scan chain to serve debugging purposes without permanently impacting timing constraints, as the dumping operation occurs in dedicated debug cycles rather than affecting continuous operational timing
Data Source
AI summary
An integrated circuit comprises a test interface, an embedded in-circuit emulator, a circuit-under-debugging, and a memory. The embedded in-circuit emulator is used for software debugging via the test interface. The circuit-under-debugging comprises a scan chain dumping states of every delayed flip-flop (DFF) out of the circuit-under-debugging. The memory stores the states from the scan chain and transfers the states to a computer via the test interface.