Scan DFT Circuit Reducing Test Data Volume
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Solution Overview
Problem
Conventional scan chain techniques for Design-for-Testability (DFT) in integrated circuits require significant memory and test time, producing large vector sets, which are inefficient and resource-intensive.
Innovation Solution
The proposed scan DFT circuit employs a memory core logic unit, input and output units with multiplexers and latches, and a control unit that operates in NORMAL, SHIFT, and CAPTURE modes, utilizing shared components to reduce chip area and component count, and implements XOR gates for input vector compression to minimize test data volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional scan chain techniques are used for DFT, then defect detection capability is achieved, but test data volume and memory requirements increase significantly
Solution Approach 1:
The patent combines multiple scan chains into a unified scan structure where scan cells are organized in groups that share common control logic and multiplexers. This merging reduces the overall test data volume by eliminating redundant control signals and allowing parallel testing of multiple chains with compressed test patterns.
Solution Approach 2:
The scan cells are designed with multi-functional capability, serving both as functional circuit elements during normal operation and as testable units during DFT mode. The universal design allows the same hardware to perform both computation and testing functions, reducing the need for separate test-specific components and thereby reducing overall test data requirements.
2Reliability
If conventional scan chain techniques are used for DFT, then every latch can be tested, but test time increases significantly
Solution Approach 1:
The scan chains are segmented into multiple groups or banks, each controlled by independent control logic. This segmentation allows parallel testing of different groups simultaneously, significantly reducing the overall test time while maintaining complete latch coverage. Each segment can be tested independently or in combination with others.
Solution Approach 2:
The patent implements a continuous testing mechanism where scan cells remain in test mode throughout the testing process without requiring intermediate reset or reconfiguration steps. The unified control logic enables seamless transition between testing different segments, eliminating idle time and maintaining continuous useful action throughout the test sequence.
3Ease of operation
If conventional scan chain techniques are used for DFT, then testability is improved, but chip area increases due to additional components
Solution Approach 1:
Multiple scan chains share common control logic, multiplexers, and output registers, eliminating the need for duplicate components for each chain. This merging approach maintains full testability of all latches while significantly reducing the chip area required for DFT infrastructure compared to fully independent scan chains.
Solution Approach 2:
The control logic and supporting components are designed with universal functionality, serving multiple scan chains simultaneously. The multiplexers and control units can dynamically configure and control different groups of scan cells, providing the same testability benefits as dedicated components would offer but with fraction of the area overhead.
4Measurement precision
If conventional scan chain techniques are used for DFT, then complete state observation is achieved, but vector set size increases
Solution Approach 1:
The patent transitions from testing individual latches in isolation to testing groups of latches in a multi-dimensional array structure. By organizing scan cells in banks and groups with hierarchical control, the system can observe complete system states through fewer, more comprehensive test vectors that exploit the spatial arrangement and interrelationships between latches.
Solution Approach 2:
The unified control logic acts as an intermediary that coordinates testing across multiple scan chains and groups, enabling complete state observation through compressed test sequences. The control logic generates and manages test patterns that systematically exercise all latches while reducing the total vector count by exploiting the structured organization of scan cells.
Data Source
AI summary
An IC includes a memory core logic unit, an output unit, and an input unit. The memory logic unit is coupled to a plurality of bit cells configured to control read and write of data to and from the plurality of bit cells. The input unit is formed on the integrated circuit. The output unit is formed on the integrated circuit. The input unit includes a second plurality of multiplexers for signal selection, at least one lock up latch for storing data and configured to increase a hold time for the data, and at least one shadow latch configured to store a copy of the data stored in the at least one lock up latch. The output unit includes a first plurality of multiplexers for signal selection and at least one high phase pass latch for storing data.