Multi-Phase Scan Drive Circuit for High-Frame-Rate Micro LED Panels

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Solution Overview

Problem

Micro LED display technology faces challenges in circuit design due to spatial limitations, bidirectional scan circuits, signal transmission complexity, and signal width and clock issues, which affect circuit performance and efficiency.

Innovation Solution

A scan driving circuit is designed with a startup circuit, logic gate, pull-down circuit, and multiple output circuits to optimize signal generation and transmission, reduce circuit complexity, and enhance frame rate support.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If multiple sets of scan driver circuits are merged into a multi-phase scan driver circuit, then the circuit layout space is reduced and the number of pins is decreased, but the circuit complexity and signal transmission complexity increase

Engineering Contradiction:
Improvecircuit layout spaceVSAvoidcircuit complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The scan driver circuit is divided into multiple independent output circuits (first output circuit, second output circuit, third output circuit, fourth output circuit), each capable of generating scan signals independently. This segmentation allows the circuit to maintain reduced layout space while managing complexity through modular design, where each segment handles specific phase signals separately.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple scan driver circuits are merged into a single multi-phase scan driver circuit that generates multiple phases of scan signals simultaneously. This merging reduces the overall circuit layout space and decreases the number of external pins required, while the internal complexity is managed through the segmented output circuit architecture.

Inventive Principle:
Principle #5Merging (Combining)

2Device complexity

If the signal width of the clock signal is limited, then the circuit design is simpler, but the frame rate performance is affected

Engineering Contradiction:
Improvecircuit design complexityVSAvoidframe rate
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The circuit uses dynamic clock signal distribution where a single clock signal is dynamically divided into multiple phases through the output circuits. This dynamic phase generation allows the circuit to maintain simple design (single clock input) while achieving high frame rates through efficient multi-phase signal generation that drives the display panels at higher speeds.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If bidirectional scan circuits are removed to simplify circuit design, then the circuit becomes simpler, but the circuit pullback functions are affected

Engineering Contradiction:
Improvecircuit design simplicityVSAvoidcircuit pullback function
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

Instead of using traditional bidirectional scan circuits with pullback functions, the invention inverts the approach by using unidirectional scan circuits that scan from first to second direction only. The display panel is designed to accommodate this unidirectional scanning pattern, eliminating the need for complex bidirectional control while maintaining reliable display operation through the inverted scanning architecture.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS12387666B2Scan drive circuit
Publication Date: 2025.08.12 AU OPTRONICS CORP
  • US12387666B2 patent drawing
  • US12387666B2 patent drawing
  • US12387666B2 patent drawing

AI summary

A scanning drive circuit includes: a start-up circuit, activated based on a start-up signal or a previous stage output signal to pre-charge a first internal node; a logic gate operating based on the start-up signal or the previous stage output signal and a first output signal to control a second voltage at a second internal node; a pull-down circuit determining whether to pull down a first voltage of the first internal node based on the second voltage of the second internal node; and a plurality of output circuits pre-charging a third internal node based on the first voltage of the first internal node and generating a plurality of output signals based on a scanning clock signal or a plurality of clock signals, and further determining whether to pull down the output signals based on the second voltage of the second internal node.