Scan Driver Asymmetrical Circuit Segmentation for Display Devices

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Solution Overview

Problem

Conventional embedded scan drivers in high-resolution and large-screen display devices suffer from propagation delay and gate floating issues, leading to deteriorated picture quality and circuit reliability.

Innovation Solution

The implementation of a scan driver with asymmetrical circuit configurations, including a shift register and a level shifter, where the shift register is arranged in non-display areas and connected to scan lines, and a compensation circuit unit that maintains scan low voltage based on node voltages from neighboring stage circuits, addresses propagation delay and gate floating.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If an embedded scan driver is used in high-resolution and large-screen display devices, then the display device can be integrated, but propagation delay and gate floating occur leading to deteriorated picture quality

Engineering Contradiction:
Improveintegration of scan driverVSAvoidpicture quality
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The scan driver is divided into multiple stage circuit units (first through fourth stages) distributed across different non-display areas. Each stage circuit unit independently drives specific scan lines, segmenting the overall scanning function to reduce propagation delay and prevent gate floating in any single region.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent utilizes both left and right non-display areas (spatial dimension) to distribute stage circuit units. This two-dimensional arrangement allows scan signals to be generated from multiple locations simultaneously, reducing the distance signals must travel and minimizing propagation delay effects.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If the scan driver is embedded in the display panel, then integration is improved, but gate floating occurs due to circuit characteristics

Engineering Contradiction:
Improveembedded scan driver integrationVSAvoidgate voltage stability
Core Design Contradiction:
Device complexityVSStability of the object's composition

Solution Approach 1:

The compensation circuit units monitor node voltages in the stage circuit units and provide compensating signals to maintain stable gate voltages. This feedback mechanism detects and corrects gate floating conditions by adjusting voltages based on actual circuit state.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The compensation circuit units act as intermediary elements between the stage circuit units and the scan lines. They buffer and stabilize voltage levels, preventing direct exposure of scan lines to voltage fluctuations and gate floating effects.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If conventional embedded scan driver configuration is used, then manufacturing is simplified, but propagation delay deteriorates picture quality

Engineering Contradiction:
Improvescan driver implementationVSAvoidpicture quality
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent employs asymmetrical arrangement of stage circuit units and compensation circuit units in the non-display areas. This asymmetrical configuration optimizes signal paths and compensation effectiveness, achieving improved picture quality while maintaining manufacturability through standard thin film transistor processes.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS9818353B2Scan driver ADN display device using the same
Publication Date: 2017.11.14 LG DISPLAY CO LTD
  • US9818353B2 patent drawing
  • US9818353B2 patent drawing
  • US9818353B2 patent drawing

AI summary

Disclosed is a display device that may include a display panel, a data driver configured to supply a data signal to the display panel, and a scan driver formed in a non-display area of the display panel, including a shift register composed of a plurality of stages and a level shifter formed outside the display panel, and configured to supply a scan signal to the display panel using the shift register and the level shifter, wherein the shift register is arranged in an output terminal of an N-th stage circuit unit formed in a first non-display area and an output terminal of an N-th compensation circuit unit formed in a second non-display area opposite the first non-display area are paired to be connected to an N-th scan line, wherein the N-th compensation circuit unit outputs a compensation signal to the N-th scan line in response to a node voltage of a neighboring stage circuit unit.