Display Scan Driver Partitioning With In-Display Buffer Circuits
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Solution Overview
Problem
The large size of the peripheral area in display apparatuses due to the inclusion of the entire scan driving circuit outside the display area affects the aesthetic appearance and increases the overall size of the device.
Innovation Solution
A portion of the scan driving circuit, including logic and buffer circuits, is integrated into the display area, reducing the size of the peripheral area and improving the aesthetic appearance by overlapping buffer circuits with pixel circuits and light-emitting devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the entire scan driving circuit is arranged in the peripheral area outside the display area, then the scan driving circuit can be easily implemented and controlled, but the peripheral area size increases, affecting aesthetic appearance and overall device size
Solution Approach 1:
The scan driving circuit is divided into two parts: a logic circuit unit arranged in the peripheral area and a buffer circuit unit arranged in the display area. This segmentation allows the driving circuit to be distributed across both regions, reducing the peripheral area size while maintaining ease of implementation through modular architecture.
Solution Approach 2:
The buffer circuit unit is positioned in the display area, utilizing the vertical dimension of the substrate. By stacking the buffer circuit unit over the pixel circuit in the third dimension (vertically), the patent reduces the horizontal footprint of the peripheral area while maintaining functional connectivity.
2Area of stationary object
If the buffer circuit unit is arranged in the display area overlapping with pixel circuits, then the peripheral area size is reduced, but the display area layout becomes more complex
Solution Approach 1:
The buffer circuit unit is positioned in the display area, utilizing the vertical dimension of the substrate. By stacking the buffer circuit unit over the pixel circuit in the third dimension (vertically), the patent reduces the horizontal footprint of the peripheral area while maintaining functional connectivity.
Solution Approach 2:
The buffer circuit unit is nested within the display area footprint, with the buffer circuit unit overlapping the pixel circuit in the vertical dimension. This nesting approach allows the buffer circuit unit to share the horizontal space with the pixel circuit while maintaining separate functional layers.
3Device complexity
If the logic circuit unit and buffer circuit unit are separated into different areas, then the signal transmission path is simplified, but the overall device size increases
Solution Approach 1:
The scan driving circuit is divided into two parts: a logic circuit unit arranged in the peripheral area and a buffer circuit unit arranged in the display area. This segmentation allows the driving circuit to be distributed across both regions, reducing the peripheral area size while maintaining ease of implementation through modular architecture.
Solution Approach 2:
The buffer circuit unit is positioned in the display area, utilizing the vertical dimension of the substrate. By stacking the buffer circuit unit over the pixel circuit in the third dimension (vertically), the patent reduces the horizontal footprint of the peripheral area while maintaining functional connectivity.
Data Source
AI summary
A display apparatus includes a substrate, a first logic circuit, a second logic circuit, a first buffer circuit, and a second buffer circuit. The substrate includes a display area and a peripheral area. The first logic circuit and second logic circuit are arranged in the peripheral area. The first buffer circuit and the second buffer circuit are arranged in the display area. The first buffer circuit is electrically connected to the first logic circuit and outputs a first scan signal. The second buffer circuit is electrically connected to the second logic circuit and outputs a second scan signal. The first scan signal and the second scan signal control transistors in a pixel circuit. In addition, a light-emitting diode arranged on the first buffer circuit and is electrically connected to the pixel circuit.