Scan Driver Clock Signal Falling Time Optimization
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Solution Overview
Problem
Existing scan drivers for display apparatuses face challenges in reducing heat emission, which can lead to overheating and affect image quality and device performance.
Innovation Solution
The proposed scan driver incorporates a design with multiple stages, each featuring a node controller and output controllers with specific transistor configurations to manage clock signals, ensuring optimized rising and falling times, and on-voltage periods to minimize heat emission while maintaining image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional scan driver designs are used, then scan signal generation is achieved, but heat emission increases causing overheating and affecting image quality
Solution Approach 1:
The patent applies parameter changes by differentiating the falling times of clock signals. Specifically, the first clock signal has a shorter falling time compared to the second and third clock signals, while maintaining identical rising times. This parameter differentiation optimizes the switching characteristics of transistors, reducing power dissipation and heat emission during the falling edge transitions, thereby addressing the thermal management issue without compromising image quality
2Productivity
If multiple clock signals are used for scan signal generation, then scan driving capability is improved, but heat emission increases
Solution Approach 1:
The patent applies local quality by assigning different falling time characteristics to different clock signals based on their specific functions. The first clock signal (for normal scan) has a shorter falling time for faster response, while the second and third clock signals (for overlay scan) have longer falling times to reduce power consumption. This localized optimization allows multiple scan modes to coexist with reduced overall heat emission
Data Source
AI summary
A scan driver includes stages, and first to third clock signals are applied to the stages, respectively. A falling time of the first clock signal is shorter than falling times of the second and third clock signals.