Scan Driver Wire Layout for Low-Delay Display Clock Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Delays in signal transmission and voltage drops in wires within the driving circuit of display devices can affect the action of pixel circuits and image quality, leading to suboptimal performance.
Innovation Solution
The implementation of a scan driver with specific transistor configurations and wire width optimizations, where wider wires for clock signals and voltage transfer reduce RC delay and minimize signal delays, thereby enhancing pixel circuit action and image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire width is increased to reduce signal delay and voltage drop, then signal transmission quality is improved, but device area and manufacturing complexity increase
Solution Approach 1:
The patent applies different wire widths to different signal paths based on their specific requirements. Clock signal wires are made wider to reduce RC delay and voltage drop, while other signal wires use standard widths. This localized optimization improves signal transmission quality where needed without unnecessarily increasing overall device complexity and area.
2Loss of time
If wire width is increased to reduce RC delay, then signal delay is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent selectively increases wire width only for clock signal paths where RC delay is critical, while maintaining standard wire widths for other signals. This localized approach reduces signal delay in critical paths without uniformly increasing manufacturing precision requirements across the entire device, thereby balancing performance improvement with manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces signal delays and voltage drops, improving the performance of pixel circuits and overall image quality by optimizing wire resistance and signal transmission efficiency.
Implementation Method 1
A width of a first wire configured to transfer a clock signal and a width of a second wire configured to transfer a scan signal are larger than at least one of a width of a third wire configured to transfer an initialization signal and a width of a fourth wire configured to transfer a data signal
Data Source
AI summary
Provided is a scan driving circuit including a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits including: a first transistor configured to receive a prior scan signal in synchronization with a first clock signal and to respond to an enable level of the prior scan signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal; a second transistor coupled between the first transistor and a first voltage; and a third transistor coupled to a gate of the second transistor and configured to be turned on by a first signal. A width of a first wire configured to transfer the first clock signal and a width of a second wire configured to transfer the second clock signal are larger than that of a third wire configured to transfer the first signal.