Scan Driver Clock Selection for 1/2 HT Pulse Timing
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Solution Overview
Problem
Conventional scan drivers for organic light emitting displays face challenges in generating scan signals that effectively drive subpixels with compensation circuits, particularly in ensuring proper synchronization and timing for optimal image display.
Innovation Solution
A scan driver with logic circuitry that receives start pulses and generates pulse signals with a ½ horizontal time delay, utilizing clock selectors and shift registers to output either a first clock or its inversion, ensuring synchronized pulse signals for driving subpixels, thereby adjusting the horizontal time period for improved image display.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional scan driver outputs scan signals for 1 horizontal time period, then the scan driver can drive standard display panels, but it cannot properly drive subpixels with compensation circuits that require 1/2 HT period signals
Solution Approach 1:
The scan driver dynamically switches between two clock signals (first clock and second clock which is an inversion of the first clock) based on the type of subpixel being driven. This dynamic clock selection enables the driver to adapt its signal period - using the first clock for standard subpixels requiring 1 HT period and the second clock for compensation circuit subpixels requiring 1/2 HT period, thereby resolving the contradiction between versatility and complexity
Solution Approach 2:
The invention changes the temporal parameter of the clock signal by providing two distinct clock signals with different phases. By selecting between these clock signals, the scan driver can change the effective period of generated scan signals from 1 HT to 1/2 HT, enabling compatibility with different subpixel types without increasing device complexity
2Reliability
If pulse signals are generated with 1/2 horizontal time delay, then synchronization for compensation circuits is achieved, but the timing coordination becomes more complex
Solution Approach 1:
The invention introduces a clock selection mechanism as an intermediary between the clock signals and the shift registers. This intermediary selects between the first clock and its inverted second clock, thereby controlling the phase and timing of generated pulse signals. This intermediary approach achieves precise 1/2 HT synchronization for compensation circuits while keeping the timing control logic manageable through systematic clock selection rather than complex individual pulse timing
Data Source
AI summary
A scan driver for an organic light emitting display includes logic circuitry to receive a plurality of start pulses and either a first clock or a second clock that is an inversion of the first clock and to generate one or more pulse signals as scan signals for driving the sub-pixels of the organic light emitting display panel, where one or more of the pulse signals are delayed by ½ horizontal time from at least another one of the pulse signals.