Scan Driver Decoder Stages for High-Resolution Flexible Arrays
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Solution Overview
Problem
Conventional scan driver circuits for flexible active matrix arrays face challenges in achieving high resolution with a small number of signal lines, as errors due to mechanical stress can affect subsequent stages, and the increase in scan lines leads to a larger area occupation, making them unsuitable for high-resolution applications.
Innovation Solution
A scan driver circuit utilizing a plurality of decoders, where each stage is driven at different timings based on combinations of decoder signals, allowing for the sequential output of scan line signals, thereby reducing the number of signal lines required and preventing error propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a decoder-type scan driver circuit is used to individually drive each scan line, then reliability is improved by preventing error propagation, but device complexity increases and area occupation increases
Solution Approach 1:
The scan driver circuit is divided into multiple independent decoder stages, where each stage drives a specific group of scan lines. This segmentation allows errors to be contained within individual stages and prevents propagation to other stages, while each decoder independently processes its assigned scan lines without requiring complex inter-stage error handling mechanisms.
2Measurement precision
If the number of scan lines increases to achieve high resolution, then measurement precision is improved, but area occupation increases making it unsuitable for flexible substrates
Solution Approach 1:
The patent employs multiple decoder stages operating in sequence to drive a large number of scan lines. Instead of requiring all scan line control signals to exist simultaneously in one dimension, the system uses temporal sequencing across multiple stages, where each stage handles a portion of the total scan lines. This dimensional transformation from spatial to temporal organization reduces the area occupation of the driver circuit while maintaining high resolution capability.
3Device complexity
If a shift register-type scan driver is used to reduce signal lines, then device complexity is reduced, but reliability deteriorates due to error propagation to subsequent stages
Solution Approach 1:
The scan driver circuit is divided into multiple independent decoder stages, where each stage drives a specific group of scan lines. This segmentation allows errors to be contained within individual stages and prevents propagation to other stages, while each decoder independently processes its assigned scan lines without requiring complex inter-stage error handling mechanisms.
4Reliability
If multiple decoders are used to individually drive scan lines, then reliability is improved, but the number of signal lines increases
Solution Approach 1:
The patent employs multiple decoder stages operating in sequence to drive a large number of scan lines. Instead of requiring all scan line control signals to exist simultaneously in one dimension, the system uses temporal sequencing across multiple stages, where each stage handles a portion of the total scan lines. This dimensional transformation from spatial to temporal organization reduces the area occupation of the driver circuit while maintaining high resolution capability.
Data Source
AI summary
A scan driver circuit for an active matrix array includes a plurality of stages and a plurality of decoders that are sequentially driven at different driving timings in a same stage based on a combination of the plural decoder signals or that are driven at the same timing in different stages where a last decoder of the plural decoders sequentially outputs a scan line signal according to a driving state of the plural decoders in each of plural stages, each of the plural decoders includes an input part, an output part and a reset part, and the input part includes a first decoding transistor, a fourth decoding transistor connected to a clock signal and second, third, fifth and sixth decoding transistors connected in series to each of the first decoding transistor and the fourth decoding transistor and connected to the plural decoder signals.