Scan Driver Transistor Segmentation for DIBL Leakage
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Solution Overview
Problem
Display devices require scan drivers that can output accurate and stabilized scan signals with reduced drain-induced barrier lowering (DIBL) phenomenon, which affects the leakage current and waveform stability in transistors.
Innovation Solution
A scan driving device with multiple stages, each comprising specific transistors and capacitors connected in series, where the gate electrodes are connected to specific nodes and voltage input terminals, allowing for controlled output of scan signals and reduction of leakage current by applying enable and clock signals during specific periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistor structures are used in scan drivers, then device complexity is reduced, but leakage current increases and waveform stability deteriorates due to DIBL phenomenon
Solution Approach 1:
The transistor structure is segmented into multiple components: a first transistor for signal input, a second transistor for clock signal control, a third transistor for voltage regulation, and a fourth transistor for output control. This segmentation allows each transistor to perform a specific function, reducing the DIBL phenomenon and improving waveform stability while controlling leakage current.
Solution Approach 2:
The patent introduces dynamic control mechanisms using clock signals and voltage input terminals that can be adjusted in real-time. The gates of the transistors are connected to nodes that receive dynamic voltage inputs, allowing the transistor characteristics to be dynamically optimized to reduce DIBL effects and leakage current during operation.
2Reliability
If more transistors and capacitors are added to reduce DIBL phenomenon, then waveform stability improves, but device complexity increases
Solution Approach 1:
Each transistor in the patent serves multiple functions: the first transistor handles signal input and initial amplification, the second transistor provides clock signal control and timing, the third transistor regulates voltage levels, and the fourth transistor controls output. This multi-functionality reduces the need for additional dedicated components, maintaining scan signal accuracy while controlling overall device complexity.
Solution Approach 2:
The patent uses capacitors connected to voltage input terminals to maintain equipotential conditions at critical nodes, ensuring stable voltage levels throughout the circuit. This approach improves scan signal accuracy by reducing voltage fluctuations without requiring complex voltage regulation circuits for each transistor.
3Productivity
If transistor size is reduced to increase integration density, then productivity improves, but DIBL phenomenon worsens and leakage current increases
Solution Approach 1:
The patent applies different structural configurations to different transistors within the same circuit. The first transistor has its gate connected to a first node for signal input, the second transistor's gate is connected to a second node for clock control, the third transistor receives voltage input, and the fourth transistor controls output. This local differentiation allows each transistor to be optimized for its specific function, maintaining signal stability even at reduced sizes for higher integration density.
Solution Approach 2:
The patent introduces intermediate nodes and capacitors between the transistors that act as mediators to buffer and stabilize signals. These intermediate elements compensate for the increased DIBL effects and leakage current that occur with smaller transistor sizes, allowing high integration density while maintaining signal stability through the mediating effect of the additional circuit elements.
Data Source
AI summary
A scan driver and display device using the same are disclosed. In one aspect, the scan driver includes a plurality of stages. Each stage includes a first transistor electrically connected between a first voltage input terminal and an output terminal, wherein the first transistor comprises a gate electrode electrically connected to a first node. Each stage also includes a second transistor electrically connected between the output terminal and a second clock signal input terminal and having a gate electrode electrically connected to a second node. Furthermore, each stage includes third and fourth transistors electrically connected in series. Each stage further includes a fifth transistor having first and second electrodes and a gate electrode electrically connected to the second node, the first electrode is electrically connected between the third and fourth transistors, and the second electrode is electrically connected to a second voltage input terminal configured to receive a second voltage.